73M1903 MODEM ANALOG FRONT END DEMO BOARD User’s Manual
Revision 1.2
13 of 32
© Copyright 2005 TERIDIAN Semiconductor Corporation
SCLK
SDOUT
SDIN
FSB
TXD
RXD
CTRL-DI
CTRL-DO
TXD
RXD
CTRL-DI
CTRL-DO
CONTROL FRAME
DATA FRAME
ONE SAMPLE PERIOD
CONTROL FRAME
DATA FRAME
SCLK
SDOUT
SDIN
FSB
TXD
RXD
TXD
RXD
CTRL-DI
CTRL-DO
D0=0
D0=1
TXD
RXD
TXD
RXD
D0=0
ONE SAMPLE PERIOD
HARDWARE CONTROLLED CONTROL FRAME
SOFTWARE CONTROLLED CONTROL FRAME
Figure 2-3: Serial Port Timing
2.2 73M1903 REGISTER MAP
The following table shows the memory map of addressable registers in the 73M1903. Each register and
bits can be read or written by a host processor or a DSP using the control frames over the MAFE
interface. All registers and their bits are described in detail in 73M1903 datasheet. For more information,
please refer to the datasheet.
ADRESS Default
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
00 08h
ENFE - TXBST1
TXBST0
TXDIS
RXG1 RXG0
RXGAIN
01 00h
TMEN DIGLB ANALB
INTLB - RXPULL
SPOS HC
02
FFh
GPIO7
GPIO 6
GPIO 5
GPIO 4
GPIO 3
GPIO 2
GPIO 1
GPIO 0
03 FFh DIR7 DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIR0
04 00h
ENGPIO7
ENGPIO6
ENGPIO5
ENGPIO4 ENGPIO3 ENGPIO2 ENGPIO1 ENGPIO0
05 00h
POL7 POL6 POL5 POL4 POL3 POL2 POL1 POL0
06 40h
Rev3 Rev2 Rev1 Rev0 - Trim(2)
Trim(1)
Trim(0)
07
00h
- - - - - - - -
08 00h Pseq7 Pseq6 Pseq5 Pseq4 Pseq3 Pseq2 Pseq1 Pseq0
09 0Ah
Prst2 Prst1 Prst0 Pdvsr4 Pdvsr3 Pdvsr2 Pdvsr1 Pdvsr0
0A 22h
Ichp3 Ichp2 Ichp1 Ichp0 FL Kvco2 Kvco1 Kvco0
0B 12h
Unused
Ndvsr6 Ndvsr5
Ndvsr4 Ndvsr3 Ndvsr2 Ndvsr1 Ndvsr0
0C 00h Nseq7 Nseq6 Nseq5 Nseq4 Nseq3 Nseq2 Nseq1 Nseq0
0D C0h Xtal1 Xtal0 LokdetEn
ThLk0 - Nrst2 Nrst1 Nrst0
0E
00h
Frcvco
PwdnPLL
Lokdet
- - - - -
0F-7F
- - - - - - - -
Table 2-1: 73M1903 Demo Board jumpers and connectors
