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TR4 User Manual

38

www.terasic.com

March 30, 2017

mem_dq[6]

DDR3 Data [6]

SSTL-15 Class I

PIN_D16

mem_dq[7]

DDR3 Data [7]

SSTL-15 Class I

PIN_E16

mem_dq[8]

DDR3 Data [8]

SSTL-15 Class I

PIN_N17

mem_dq[9]

DDR3 Data [9]

SSTL-15 Class I

PIN_M17

mem_dq[10]

DDR3 Data [10]

SSTL-15 Class I

PIN_K17

mem_dq[11]

DDR3 Data [11]

SSTL-15 Class I

PIN_L16

mem_dq[12]

DDR3 Data [12]

SSTL-15 Class I

PIN_P16

mem_dq[13]

DDR3 Data [13]

SSTL-15 Class I

PIN_P17

mem_dq[14]

DDR3 Data [14]

SSTL-15 Class I

PIN_J17

mem_dq[15]

DDR3 Data [15]

SSTL-15 Class I

PIN_H17

mem_dq[16]

DDR3 Data [16]

SSTL-15 Class I

PIN_N22

mem_dq[17]

DDR3 Data [17]

SSTL-15 Class I

PIN_M23

mem_dq[18]

DDR3 Data [18]

SSTL-15 Class I

PIN_J25

mem_dq[19]

DDR3 Data [19]

SSTL-15 Class I

PIN_M24

mem_dq[20]

DDR3 Data [20]

SSTL-15 Class I

PIN_R22

mem_dq[21]

DDR3 Data [21]

SSTL-15 Class I

PIN_P22

mem_dq[22]

DDR3 Data [22]

SSTL-15 Class I

PIN_K24

mem_dq[23]

DDR3 Data [23]

SSTL-15 Class I

PIN_J24

mem_dq[24]

DDR3 Data [24]

SSTL-15 Class I

PIN_A27

mem_dq[25]

DDR3 Data [25]

SSTL-15 Class I

PIN_A28

mem_dq[26]

DDR3 Data [26]

SSTL-15 Class I

PIN_C29

mem_dq[27]

DDR3 Data [27]

SSTL-15 Class I

PIN_C30

mem_dq[28]

DDR3 Data [28]

SSTL-15 Class I

PIN_C27

mem_dq[29]

DDR3 Data [29]

SSTL-15 Class I

PIN_D27

mem_dq[30]

DDR3 Data [30]

SSTL-15 Class I

PIN_A31

mem_dq[31]

DDR3 Data [31]

SSTL-15 Class I

PIN_B31

mem_dq[32]

DDR3 Data [32]

SSTL-15 Class I

PIN_G27

mem_dq[33]

DDR3 Data [33]

SSTL-15 Class I

PIN_G29

mem_dq[34]

DDR3 Data [34]

SSTL-15 Class I

PIN_F28

mem_dq[35]

DDR3 Data [35]

SSTL-15 Class I

PIN_F27

mem_dq[36]

DDR3 Data [36]

SSTL-15 Class I

PIN_E28

mem_dq[37]

DDR3 Data [37]

SSTL-15 Class I

PIN_D28

mem_dq[38]

DDR3 Data [38]

SSTL-15 Class I

PIN_H26

mem_dq[39]

DDR3 Data [39]

SSTL-15 Class I

PIN_J26

mem_dq[40]

DDR3 Data [40]

SSTL-15 Class I

PIN_F19

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Summary of Contents for TR4

Page 1: ...TR4 User Manual 1 www terasic com March 30 2017 y94 ...

Page 2: ...NERAL USER INPUT OUTPUT 18 2 5 HIGH SPEED MEZZANINE CARDS 20 2 6 GPIO EXPANSION HEADERS 32 2 7 DDR3 SO DIMM 36 2 8 CLOCK CIRCUITRY 40 2 9 PCI EXPRESS 45 2 10 FLASH MEMORY 48 2 11 SSRAM MEMORY 51 2 12 TEMPERATURE SENSOR AND FAN 53 2 13 POWER 53 2 14 SECURITY 54 2 15 USING EXTERNAL BLASTER 54 CHAPTER 3 CONTROL PANEL 56 3 1 CONTROL PANEL SETUP 56 3 2 CONTROLLING THE LEDS 60 3 3 SWITCHES AND PUSH BUTT...

Page 3: ...ER 71 4 1 INTRODUCTION 71 4 2 GENERAL DESIGN FLOW 72 4 3 USING TR4 SYSTEM BUILDER 73 CHAPTER 5 EXAMPLES OF ADVANCED DEMONSTRATION 83 5 1 BREATHING LEDS 83 5 2 EXTERNAL CLOCK GENERATOR 84 5 3 HIGH SPEED MEZZANINE CARD HSMC 90 5 4 DDR3 SDRAM 1GB 92 5 5 DDR3 SDRAM 4GB 96 ADDITIONAL INFORMATION 100 ...

Page 4: ...ice and supported by industry standard peripherals connectors and interfaces that offer a rich set of features that is suitable for a wide range of compute intensive applications The advantages of the Stratix IV GX FPGA platform with integrated transceivers have allowed the TR4 to be fully compliant with version 2 0 of the PCI Express standard This will accelerate mainstream development of PCI Exp...

Page 5: ...SMC connectors two with transceiver support Two 40 pin GPIO expansion headers shares pins with HSMC Port C Two external PCI Express 2 0 x4 lane connectors Memory DDR3 SO DIMM socket 4GB Max 64MB FLASH 2MB SSRAM General User Input Output Four LEDs Four push buttons Four slide switches Clock system On board 50MHz oscillator Three on board programmable PLL timing chips SMA connector pair for differen...

Page 6: ... w Figure 1 1 and Figure 1 2 show the top and bottom view of the TR4 board It depicts the layout of the board and indicates the location of the connectors and key components Users can refer to these figures for relative location when the connectors and key components are introduced in the following chapters Figure 1 1 TR4 Board View Top ...

Page 7: ...iew Bottom 1 1 4 4 B Bl lo oc ck k D Di ia ag gr ra am m Figure 1 3 shows the block diagram of the TR4 board To provide maximum flexibility for the users all key components are connected with the Stratix IV GX FPGA device allowing the users to implement any system design ...

Page 8: ...17 Figure 1 3 TR4 Block Diagram Below is more detailed information regarding the blocks in Figure 1 3 Stratix IV GX FPGA EP4SGX230C2 228 000 logic elements LEs 17 133 total memory Kb 1 288 18x18 bit multipliers blocks 2 PCI Express hard IP blocks ...

Page 9: ...vice and USB Blaster Circuit MAXII CPLD EPM2210 System Controller and Fast Passive Parallel FPP configuration On board USB Blaster for use with the Quartus II Programmer Programmable PLL timing chip configured via MAX II CPLD Supports JTAG mode Memory Devices 64MB Flash 32M x16 with a 16 bit data bus 2MB SSRAM 512K x 32 DDR3 SO DIMM Socket Up to 4GB capacity Maximum memory clock rate at 533MHz The...

Page 10: ...ernal clock input SMA connector for clock output Two PCI Express x4 Edge Connectors Support connection speed of Gen1 at 2 5Gbps lane to Gen2 at 5 0Gbps lane Support downstream mode Six High Speed Mezzanine Card HSMC Connectors Two HSMC ports include 16 pairs of CDR based transceivers at data rates of up to 6 5Gbps Among HSMC Port A to D there are 55 true LVDS TX channels to 1 6Gbps and 17 emulated...

Page 11: ... Port C Configurable I O standards 1 5V 1 8V 2 5V 3 0V Power Standalone DC 19V input Other Temperature Sensor Cooling Fan 1 1 5 5 A As ss se em mb bl ly y Attach the included rubber silicon foot stands as shown in Figure 1 4 to each of the four copper stands on the TR4 board Figure 1 4 Mount Silicon Foot Stands ...

Page 12: ...ts Key Features Before You Begin Software Installation Development Board Setup Programming the Stratix IV GX Device Programming through Flash 2 2 1 1 C Co on nf fi ig gu ur ra at ti io on n O Op pt ti io on ns s JTAG FPGA Programming with USB Blaster The USB blaster is implemented on the TR4 board to provide a JTAG configuration through the on board USB to JTAG configuration logic through the type...

Page 13: ...ion Scheme JTAG FPGA Programming with External Blaster The TR4 board supports JTAG programming over external blaster via J2 To use this interface users need to solder a 2x5 pin connector 2 54mm pitch to J2 Make sure JP7 is open to bypass the JTAG interface of HSMC Flash Programming The TR4 development board contains a common Flash interface CFI memory to meet the demands for larger FPGA configurat...

Page 14: ...limit the steps that are taken when users program the flash memory on the TR4 Software Requirements Quartus II 11 1 or later Nios II IDE 11 1 or later Program_Flash folder contents Program_Flash bat Program_Flash pl Program_Flash sh tr4_default_flash_loader sof boot_loader_cfi srec Before you use the program_Flash bat batch file to program the flash memory make sure the TR4 is ...

Page 15: ...o program convert in the Program_Flash directory Programming Flash Memory with sof using Program_Flash bat 1 Launch the program_Flash bat batch file from the directory demonstrations TR4_ Stratix device TR4_Default_Flash_Loaderr Program_Flash of the TR4 system CD ROM 2 The Flash program tool shows the menu options Figure 2 3 Flash Program Tools 3 Select option 2 ...

Page 16: ...TR4 User Manual 13 www terasic com March 30 2017 Figure 2 4 Option 2 4 Enter the sof file name to be programmed onto the flash memory Figure 2 5 Enter sof Name to Program ...

Page 17: ...xtracting Option bits SREC Extracting FPGA Image SREC and Deleting intermediate files If these lines don t appear on the windows command programming on the flash memory is not successfully set up Please make sure Quartus II 11 1 and Nios II 11 1 IDE or later is used Figure 2 6 Loading sof File 6 Erasing Flash ...

Page 18: ...TR4 User Manual 15 www terasic com March 30 2017 Figure 2 7 Erasing Flash 7 Programming Flash Figure 2 8 Programming Flash 8 Programming complete ...

Page 19: ...face on all the HSMC connectors The JTAG signals on each HSMC connector can be removed or included in the active JTAG chain via DIP switches Table 2 1 lists the position of the DIP switches and their associated interfaces Note that if the JTAG interface on HSMC connector is enabled make sure that the active JTAG chain must be a closed loop or the FPGA may not be detected Section 2 5 will give an e...

Page 20: ...SMD BOT in chain OFF Bypass HSMD BOT OFF SW6 position 1 HSMCE_TOP ON HSME TOP in chain OFF Bypass HSME TOP OFF position 2 HSMCF_TOP ON HSMF TOP in chain OFF Bypass HSMF TOP OFF 2 2 3 3 S St ta at tu us s E El le em me en nt ts s The TR4 includes status LEDs Please refer Table 2 2 for the status of the LED indicator Table 2 2 LED Indicators Board Reference LED name Description D13 HSMC Port E prese...

Page 21: ... six push buttons that allow you to interact with the Stratix IV GX FPGA Each of these buttons is debounced using a Schmitt Trigger circuit as indicated in Figure 2 10 Each push button provides a high logic level or a low logic level when it is not pressed or pressed respectively active low Table 2 3 lists the board references signal names and their corresponding Stratix IV GX device pin numbers F...

Page 22: ... FPGA respectively Table 2 5 lists the board references signal names and their corresponding Stratix IV GX device pin numbers Table 2 5 Slide Switches Pin Assignments Schematic Signal Names and Functions Name Locate Description I O Standard Stratix IV GX Pin Number SW0 SLIDE SW Provides high logic level when in the UP position VCCIO_HSMF PIN_AH18 SW1 SLIDE SW VCCIO_HSMF PIN_AH19 SW2 SLIDE SW VCCIO...

Page 23: ...ector Groups There are ten HSMC connectors on the TR4 board are divided into 6 groups HSMC A HSMC B HSMC C HSMC D HSMC E and HSMC F Each group has a male and female HSMC port on the top and bottom side of the TR4 board except HSMC E and HSMC F In addition both the male and female HSMC connector share the same I O pins besides JTAG interface and high speed serial I O transceivers Caution DO NOT con...

Page 24: ...ich can run up to 1 6Gbps The LVDS transmitter on HSMC Port B and C contain true and emulated LVDS channels The emulated LVDS channels use two single ended output buffers and external resistors as shown in Figure 2 12 The associated I O standard of these differential FPGA I O pins in the Quartus II project should be set to LVDS_E_3R Emulated LVDS I O data rates can reach speeds up to 1 1Gbps The f...

Page 25: ...o it lists the numbers of LVDS receivers needed to assemble external input termination resistors on each HSMC ports Table 2 8 shows all the external input differential resistors for LVDS receivers on HSMC Port B and C The factory default setting is not installed Finally because HSMC Port C shares FPGA I O pins with GPIO headers so the LVDS performance can only support a data rate of up to 500Mbps ...

Page 26: ...8 11 9 18 9 NA Needed External Input Termination Resistors 0 7 9 0 NA NA Table 2 8 Distribution of the Differential Termination Resistors for HSMC Connector HSMC Differential Net Reference name of the differential termination resistor HSMB_RX_p 11 R333 HSMB_RX_p 12 R318 HSMB_RX_p 13 R312 HSMB_RX_p 14 R311 HSMB_RX_p 15 R303 HSMB_RX_p 16 R315 HSMB_D 1 R332 HSMC_RX_p 0 R314 HSMC_RX_p 1 R316 HSMC_RX_p...

Page 27: ...rt On Chip differential termination please solder input termination resistors on R299 and R300 respectively when using HSMC_CLKIN_p2 n2 and HSMA_CLKIN_p2 n2 as LVDS signals Table 2 9 HSMC clock interface distribution HSMC Clock in out pin name FPGA Clock Input Pin Placement HSMA HSMB HSMC HSMD HSME HSMF CLKIN0 I O I O I O CLK1n I O CLK5p CLKIN_p1 CLK9p I O CLK2p CLK0p CLK11p CLK6p CLKIN_n1 CLK9n I...

Page 28: ...s are used as general purpose I O the maximum data rate is 60Mbps I O through the Level Translator There is a pin named HSMD_OUT0 on HSMC Port D which is connected to an FPGA 1 5V I O standard bank To meet the I O standard of adjustable specification a level translator is used between the FPGA and HSMC Port D on this net Thus the maximum data rate of this pin is 60Mbps due to the limitations of th...

Page 29: ...ds The FPGA I O standards of the HSMC ports can be adjusted by configuring the header position Each port can be individually adjusted to 1 5V 1 8V 2 5V or 3 0V via jumpers on the top right corner of TR4 board Figure 2 14 depicts the position of the jumpers and their associated I O standards Users can use 2 pin jumpers to configure the I O standard by choosing the associated positions on the header...

Page 30: ...tandard may not work properly on TR4 board due to I O standard mismatch When using custom or third party HSMC daughter cards make sure that all the pin locations are aligned to prevent shorts Using THCB HMF2 Adapter Card The purpose of the HSMC Height Extension Male to Female card THCB HMF2 included in the TR4 kit package is to increase the height of the HSMC Port C and D connector to avoid any ob...

Page 31: ...e of TR4 board are controlled by SW4 and SW6 SW5 is used to control the HSMC JTAG chain on the bottom side of the TR4 Only when multiple TR4s are stacked should the boards use this switch A document titled Using_Multi TR4_system pdf in the TR4 system CD will give an example to demonstrate how to set SW5 to connect JTAG chains together for multiple TR4 boards Finally before using the JTAG interface...

Page 32: ...TAG Chain for a Standalone TR4 If the HSMC based daughter card connected to the HSMC connector uses the JTAG interface the 4 position DIP switch SW4 or SW6 should be set to On according to the HSMC port used In this case from Figure 2 17 HSMC Port D is used so position 4 of the SW4 switch is set to On Similarly if the JTAG interface isn t used on the HSMC based daughter card position 4 of SW4 is s...

Page 33: ...30 www terasic com March 30 2017 Figure 2 17 JTAG Chain for a Daughter Card JTAG is used Connected to HSMC Port D of the TR4 Figure 2 18 JTAG chain for a Daughter Card JTAG not used Connected to HSMC Port D of the TR4 ...

Page 34: ...ce In situations where users design exceeds the capacity of the FPGA the HSMC interface can be used to connect to other FPGA system boards creating a multi FPGA scalable system Users can stack two TR4s as shown in Figure 2 19 Another option is to use a Samtec high speed cable to connect two TR4 boards See Figure 2 20 to expand your system For more information on how to use multi TR4 systems please...

Page 35: ...he TR4 consists of two 40 pin expansion headers as shown in Figure 2 21 Each header has 36 I O pins connected to the Stratix IV GX FPGA with the other 4 pins providing 5V VCC5 DC 3 3V VCC33 DC and two GND pins GPIO 0 and GPIO 1 share pins with HSMC Port C The I O standards of the GPIO headers are the same as HSMC Port C which can be configured between 1 5 1 8 2 5 and 3 0V ...

Page 36: ...TR4 User Manual 33 www terasic com March 30 2017 Figure 2 21 Pin Distribution of the GPIO Expansion Headers Finally Figure 2 22 shows the connections between the GPIO expansion headers and Stratix IV GX ...

Page 37: ...1 GPIO Expansion 0 IO 1 PIN_AG34 3 GPIO0_D2 GPIO Expansion 0 IO 2 Clock In PIN_AE35 4 GPIO0_D3 GPIO Expansion 0 IO 3 PIN_AG35 5 GPIO0_D4 GPIO Expansion 0 IO 4 PIN_AC31 6 GPIO0_D5 GPIO Expansion 0 IO 5 PIN_AH32 7 GPIO0_D6 GPIO Expansion 0 IO 6 PIN_AC32 8 GPIO0_D7 GPIO Expansion 0 IO 7 PIN_AH33 9 GPIO0_D8 GPIO Expansion 0 IO 8 PIN_AH34 10 GPIO0_D9 GPIO Expansion 0 IO 9 PIN_AJ34 13 GPIO0_D10 GPIO Exp...

Page 38: ...28 Table 2 14 GPIO Expansion Header JP10 Pin Assignments Schematic Signal Names and Functions Board Reference JP10 Schematic Signal Name Description I O Standard Stratix IV GX Pin Number 1 GPIO1_D0 GPIO Expansion 1 IO 0 Depends on I O Standard of HSMC Port C PIN_AB27 2 GPIO1_D1 GPIO Expansion 1 IO 1 PIN_AE25 3 GPIO1_D2 GPIO Expansion 1 IO 2 PIN_AB28 4 GPIO1_D3 GPIO Expansion 1 IO 3 PIN_AD25 5 GPIO...

Page 39: ...s a flexible and efficient form factor volatile memory for user applications The DDR3 SODIMM socket is wired to support a maximum capacity of 4GB with a 64 bit data bus Using differential DQS signaling for the DDR3 SDRAM interfaces it is capable of running at up to 533MHz memory clock for a maximum theoretical bandwidth up to 68Gbps Figure 2 23 shows the connections between the DDR3 SO DIMM socket...

Page 40: ... DDR3 Differential 1 5 V SSTL Class I PIN_K27 mem_ck 1 Clock p1 for DDR3 Differential 1 5 V SSTL Class I PIN_L25 mem_ck_n 0 Clock n0 for DDR3 Differential 1 5 V SSTL Class I PIN_J27 mem_ck_n 1 Clock n1 for DDR3 Differential 1 5 V SSTL Class I PIN_K28 mem_cs_n 0 DDR3 Chip Select 0 SSTL 15 Class I PIN_D23 mem_cs_n 1 DDR3 Chip Select 1 SSTL 15 Class I PIN_G28 mem_dm 0 DDR3 Data Mask 0 SSTL 15 Class I...

Page 41: ...R22 mem_dq 21 DDR3 Data 21 SSTL 15 Class I PIN_P22 mem_dq 22 DDR3 Data 22 SSTL 15 Class I PIN_K24 mem_dq 23 DDR3 Data 23 SSTL 15 Class I PIN_J24 mem_dq 24 DDR3 Data 24 SSTL 15 Class I PIN_A27 mem_dq 25 DDR3 Data 25 SSTL 15 Class I PIN_A28 mem_dq 26 DDR3 Data 26 SSTL 15 Class I PIN_C29 mem_dq 27 DDR3 Data 27 SSTL 15 Class I PIN_C30 mem_dq 28 DDR3 Data 28 SSTL 15 Class I PIN_C27 mem_dq 29 DDR3 Data ...

Page 42: ... mem_dq 59 DDR3 Data 59 SSTL 15 Class I PIN_H22 mem_dq 60 DDR3 Data 60 SSTL 15 Class I PIN_K22 mem_dq 61 DDR3 Data 61 SSTL 15 Class I PIN_D22 mem_dq 62 DDR3 Data 62 SSTL 15 Class I PIN_G22 mem_dq 63 DDR3 Data 63 SSTL 15 Class I PIN_E22 mem_dqs 0 DDR3 Data Strobe p 0 Differential 1 5 V SSTL Class I PIN_D15 mem_dqs 1 DDR3 Data Strobe p 1 Differential 1 5 V SSTL Class I PIN_K16 mem_dqs 2 DDR3 Data St...

Page 43: ...I PIN_G26 mem_ras_n DDR3 Row ADDRess Strobe SSTL 15 Class I PIN_D24 mem_we_n DDR3 Write Enable SSTL 15 Class I PIN_M27 mem_event_n DDR3 Temperature Event SSTL 15 Class I PIN_R18 mem_reset_n DDR3 Reset SSTL 15 Class I PIN_J18 mem_scl DDR3 I2C Serial Clock 1 5V PIN_H19 mem_sda DDR3 I2C Serial Data Bus 1 5V PIN_P18 Figure 2 23 Connection between DDR3 and Stratix IV GX FPGA 2 2 8 8 C Cl lo oc ck k C C...

Page 44: ...x IV GX FPGA originate from on board oscillators a 50MHz driven through the clock buffers as well as other interfaces including HSMC GPIO expansion headers share pins with HSMC Port C and SMA connectors The overall clock distribution of the TR4 is presented in Figure 2 24 ...

Page 45: ...TR4 User Manual 42 www terasic com March 30 2017 Figure 2 24 Clock Connections of the TR4 ...

Page 46: ... the clock input multiplexer allow users to use any of these clocks as a source clock to drive the Stratix IV PLL circuit through the GCLK and RCLK networks Alternatively PLLs through the GCLK and RCLK networks or from dedicated connections on adjacent top bottom and left right PLLs can also drive the PLL circuit The clock outputs of the Stratix IV GX FPGA are derived from various interfaces notab...

Page 47: ...ANK3 50MHz clock input for bank 3C 2 5 V AW22 U20 4 OSC_50_BANK4 50MHz clock input for bank 4C 2 5 V AV19 U12 4 OSC_50_BANK7 50MHz clock input for bank 7C 1 5 V A21 U13 4 OSC_50_BANK8 50MHz clock input for bank 8C 1 5 V B23 U11 6 HSMA_REFCLK_p HSMC A transceiver reference clock input LVDS AA2 U11 5 HSMA_REFCLK_n HSMC A transceiver reference clock input LVDS AA1 U5 6 HSME_REFCLK_p HSMC E transceive...

Page 48: ...base specification 2 0 that includes PHY MAC Data Link and transaction layer circuitry embedded in PCI Express hard IP blocks To use PCIe interface two external associated devices will be needed to establish link with PC First a PCIe half height add in host card with a PCIe x4 cable connector called PCA PCIe Cabling Adapter Card See Figure 2 25 will be used to plug into the PCIe slot on a mother b...

Page 49: ...TR4 User Manual 46 www terasic com March 30 2017 Figure 2 25 PCIe Cabling Adaptor PCA card Figure 2 26 PCIe External Cable ...

Page 50: ...TR4 User Manual 47 www terasic com March 30 2017 Figure 2 27 PCIe Link Setup between TR4 and PC Figure 2 28 PCI Express Pin Connection ...

Page 51: ...1 4 V PCML AG38 Table 2 17 PCIe1 Express Pin Assignments Schematic Signal Names and Functions PCIe1 4 Lane Downstream Name Description I OStandard Stratix IV GX Pin Number PCIE1_REFCLK_p PCIe1 reference clock HCSL AN2 PCIE1_PREST_n PCIe1 present Depends on HSMC Port A I O standard G8 PCIE1_WAKE_n PCIe1 wake Depends on HSMC Port A I O standard AE11 PCIE1_TX_p 0 PCIe1 data lane 1 4 V PCML AT4 PCIE1_...

Page 52: ...in output synchronous burst read operations at 40MHz with zero wait states The device defaults to asynchronous page mode read when power up is initiated or returned from reset This device is also used to store configuration files for the Stratix IV GX FPGA where the MAX II CPLD EPM2210 can access flash for FPP configuration of the FPGA using the PFL Megafunction Table 2 18 lists the flash pin assi...

Page 53: ...3 0 V PCI X PIN_AH17 FSM_A16 Address bus 3 0 V PCI X PIN_AH16 FSM_A17 Address bus 3 0 V PCI X PIN_AE17 FSM_A18 Address bus 3 0 V PCI X PIN_AG16 FSM_A19 Address bus 3 0 V PCI X PIN_H32 FSM_A20 Address bus 3 0 V PCI X PIN_H34 FSM_A21 Address bus 3 0 V PCI X PIN_G33 FSM_A22 Address bus 3 0 V PCI X PIN_F35 FSM_A23 Address bus 3 0 V PCI X PIN_N31 FSM_A24 Address bus 3 0 V PCI X PIN_M31 FSM_A25 Address ...

Page 54: ...orking applications Table 2 19 lists the SSRAM pin assignments and signal names relative to the Stratix IV GX device in terms of I O setting Table 2 19 SSRAM Memory Pin Assignments Schematic Signal Names and Functions Schematic Signal Name Description I O Standard Stratix IV GX Pin Number FSM_A2 Address bus A0 3 0 V PCI X PIN_F34 FSM_A3 Address bus A1 3 0 V PCI X PIN_D35 FSM_A4 Address bus A2 3 0 ...

Page 55: ..._D19 Data bus 3 0 V PCI X PIN_R28 FSM_D20 Data bus 3 0 V PCI X PIN_R29 FSM_D21 Data bus 3 0 V PCI X PIN_N30 FSM_D22 Data bus 3 0 V PCI X PIN_N28 FSM_D23 Data bus 3 0 V PCI X PIN_M28 FSM_D24 Data bus 3 0 V PCI X PIN_H31 FSM_D25 Data bus 3 0 V PCI X PIN_G31 FSM_D26 Data bus 3 0 V PCI X PIN_D31 FSM_D27 Data bus 3 0 V PCI X PIN_E31 FSM_D28 Data bus 3 0 V PCI X PIN_F31 FSM_D29 Data bus 3 0 V PCI X PIN_...

Page 56: ...n reset POR slave address for this sensor is 0011000b An optional 3 pin 12V header for fan control located on J10 of the TR4 board is intended to reduce the temperature of the FPGA When the temperature of the FPGA device is over the threshold value set by the users the fan will turn on automatically The pin assignments for the associated interface are listed in Table 2 20 Table 2 20 Temperature Se...

Page 57: ...designs against unauthorized copying reverse engineering and tampering of your configuration files For more information please refer to Altera s application note AN556 Using the Design Security Features in Altera FPGAs 2 2 1 15 5 U Us si in ng g E Ex xt te er rn na al l B Bl la as st te er r User can use external blaster to configure FPGA such us Ethernet Blaster To use this feature user need to i...

Page 58: ...TR4 User Manual 55 www terasic com March 30 2017 Figure 2 31 R199 R201 Position on TR4 ...

Page 59: ...king the TR4_ControlPanel exe CAUTION Please make sure Quartus II and USB Blaster Driver are installed before launching TR4 Control Panel In addition before the TR4 control panel is launched it is imperative that the fan is installed on the Stratix IV GX device to prevent excessively high temperatures on the FPGA To activate the Control Panel perform the following steps Make sure Quartus II and Ni...

Page 60: ...he Control Panel will occupy the USB port users will not be able to download any configuration file into the FPGA before you exit the Control Panel program Figure 3 1 Download sof Files to the TR4 board The Control Panel is now ready as shown in Figure 3 2 ...

Page 61: ... Panel is Ready If the connection between TR4 board and USB Blaster is not established or the TR4 board is not powered on before running the TR4_ControlPanel exe the Control Panel will fail to detect the FPGA and a warning message window will pop up as shown in Figure 3 3 ...

Page 62: ...ure 3 4 The Control Codes which performs the control functions is implemented in the FPGA board It communicates with the Control Panel window which is active on the host computer via the USB Blaster link The graphical user interface is used to issue commands to the control codes It handles all requests and performs data transfer between the computer and the TR4 board ...

Page 63: ...e from various memory types in addition to testing various components of the TR4 board 3 3 2 2 C Co on nt tr ro ol ll li in ng g t th he e L LE ED Ds s One of the functions of the Control Panel is to set up the status of the LEDs The tab window shown in Figure 3 5 indicates where you can directly turn all the LEDs on or off individually by selecting them and clicking Light All or Unlight All ...

Page 64: ... wi it tc ch he es s a an nd d P Pu us sh h B Bu ut tt to on ns s Choose the Button tab as shown in Figure 3 6 This function is designed to monitor status of switches and buttons from a graphical user interface in real time It can be used to verify the functionality of switches and buttons ...

Page 65: ...e DDR3 SO DIMM is accessed Click on the Memory tab to reach the tab window shown in Figure 3 7 A 16 bit value can be written into the DDR3 SO DIMM memory by three steps namely specifying the address of the desired location entering the hexadecimal data to be written and pressing the Write button Contents of the location can be read by pressing the Read button Figure 3 8 depicts the result of writi...

Page 66: ... the Control Panel responds with the standard Windows dialog box asking for the source file specify the desired file in the usual manner The Sequential Read function is used to read the contents of the serial configuration device and place them into a file as follows Specify the starting address in the Address box Specify the number of bytes to be copied into a file in the Length box If the entire...

Page 67: ...TR4 User Manual 64 www terasic com March 30 2017 Figure 3 7 Access DDR3 SO DIMM Memory ...

Page 68: ...or through the Control Panel The temperatures of Stratix IV GX and TR4 board are shown on the right hand side of the Control Panel When the temperature of Stratix IV GX exceeds the maximum setting of Over Temperature or Alert a warning message will be shown on the Control Panel Click Read button to get current settings for Over temperature and Alert Users can enter the maximum and minimum temperat...

Page 69: ...on the TR4 There are 3 programmable clocks for the TR4 board that generates reference clocks for the following signals HSMA_REFCLK_p n HSMB_REFCLK_p n and PGM_GXBCLK_p1 n1 The clock frequency can be adjusted to 62 5 75 100 125 150 156 25 187 5 200 250 312 5 and 625MHz Choose the PLL tab to reach the window shown in Figure 3 10 To set the desire clock frequency for the associated clock signal click...

Page 70: ... D E and F using a loopback approach Before running the loopback verification HSMC test select the desired HSMC connector to be tested Follow the instruction noted under Loopback Installation section and click on Verify Note the Control Panel HSMC loopback test does not test the transceiver signals on the HSMC interface For HSMC transceiver loopback test please refer to the demonstration section C...

Page 71: ...ation Test Performed under Control Panel 3 3 8 8 F Fa an n Choose the Fan tab to reach the window shown in Figure 3 12 This function is designed to verify the functionality of the fan components and signals Please make sure the fan is installed on the TR4 before running this function ...

Page 72: ... I In nf fo or rm ma at ti io on n For more information please click on the Information button in order to reach the window shown in Figure 3 13 Users can click Terasic Web button and TR4_Web button to reach the respective websites in order to learn more about the TR4 and Terasic Technologies ...

Page 73: ...TR4 User Manual 70 www terasic com March 30 2017 Figure 3 13 Information Tab of TR4 Control Panel ...

Page 74: ...generated Quartus II project files include Quartus II Project File qpf Quartus II Setting File qsf Top Level Design File v External PLL Controller v Synopsis Design Constraints file sdc Pin Assignment Document htm The TR4 System Builder not only can generate the files above but can also provide error checking rules to handle situations that are prone to errors The common mistakes that users encoun...

Page 75: ...ccording to their design requirements When users complete the settings the TR4 System Builder will generate two major files which include a top level design file v and the Quartus II settings file qsf The top level design file contains a top level Verilog wrapper for users to add their own design logic The Quartus II settings file contains information such as FPGA device type top level pin assignm...

Page 76: ...w the TR4 System Builder is used Install and launch the TR4 System Builder The TR4 System Builder is located in the directory Tools TR4_SystemBuilder in the TR4 System CD Users can copy the whole folder to a host computer without installing the utility Before using the TR4 System Builder execute the TR4_SystemBuilder exe on the host computer as appears in Figure 4 2 Figure 4 2 TR4 System Builder W...

Page 77: ...pe and input project name as show in Figure 4 3 Board Type Select the appropriate FPGA device according to the TR4 board which includes the EP4SGX230 and EP4SGX530 devices Project Name Specify the project name as it is automatically assigned to the name of the top level design entity Figure 4 3 TR4 Board Type and Project Name S Sy ys st te em m C Co on nf fi ig gu ur ra at ti io on n ...

Page 78: ...heck in the field provided If the component is enabled the TR4 System Builder will automatically generate the associated pin assignments including the pin name pin location pin direction and I O standards Note The pin assignments for some components for e g DDR3 require associated controller codes in the Quartus II project otherwise Quartus II will result in compilation errors Therefore do not sel...

Page 79: ...rogrammable PLL group as shown in Figure 4 5 As the Quartus II project is created System Builder automatically generates the associated PLL configuration code according to users desired frequency in Verilog which facilitates users implementation as no additional control code is required to configure the PLLs Note If users need to dynamically change the frequency they will need to modify the genera...

Page 80: ... card is connected to The System Builder will automatically generate the associated pin assignment including pin name pin location pin direction and IO standard If a customized daughter board is used users can select HSMC Default followed by changing the pin name pin direction and IO standard according to the specification of the customized daughter board If transceiver pins are not required on th...

Page 81: ...e same HSMC daughter card is selected in both HSMC A and HSMC B expansion a prefix name is required to avoid pin name duplication as shown in Figure 4 7 otherwise System Builder will prompt an error message Figure 4 7 Specify Prefix Name for HSMC Expansion Board Additionally users can choose the HSMC C GPIO as either HSMC or GPIO since the GPIO ports share pins with HSMC Port C as shown in Figure ...

Page 82: ...s clicked a GPIO Expansion window will pop up for users to select a compatible Terasic daughter card Once a daughter card selected the JP4 header diagram in the upper left hand corner of the window which configures HSMC Port C and GPIO I O standards will adjust automatically to recommend a suitable I O standard for the selected daughter card as shown in Figure 4 9 ...

Page 83: ...S Se et tt ti in ng g M Ma an na ag ge em me en nt t The TR4 System Builder also provides functions to restore a default setting loading a setting and saving users board configuration file shown in Figure 4 10 Users can save the current board configuration information into a cfg file and load it to the TR4 System Builder ...

Page 84: ...R4 System Builder will generate the corresponding Quartus II files and documents as listed in the Table 4 1 in the directory specified by the user Table 4 1 Files Generated by TR4 System Builder No Filename Description 1 Project name v Top level Verilog file for Quartus II 2 EXT_PLL_CTRL v External PLL configuration controller IP 3 Project name qpf Quartus II Project File ...

Page 85: ...mmable PLL Configuration Controller IP will be instantiated in the Quartus II top level file as listed below ext_pll_ctrl u_ext_pll_ctrl system input osc_50 OSC_50_BANK1 rstn rstn device 1 clk1_set_wr clk1_set_wr clk1_set_rd device 2 clk2_set_wr clk2_set_wr clk2_set_rd device 3 clk3_set_wr clk3_set_wr clk3_set_rd setting trigger conf_wr conf_wr 1T 50MHz conf_rd 1T 50MHz status conf_ready 2 wire in...

Page 86: ...ns tr4_ Stratix device folder from the TR4 System CD For each of demonstrations described in the following sections we give the name of the project directory for its files which are sub directories of the demonstrations tr4_ Stratix_device folder 5 5 1 1 B Br re ea at th hi in ng g L LE ED Ds s This demonstration shows how to use the FPGA to control the luminance of the LEDs by means of dividing f...

Page 87: ... 3 programmable clock generators via Texas Instruments chips CDCM61001RHBT x 2 CDCM61004RHBT with the ability to specify the clock frequency individually as well as addressing the input reference clock for the Stratix IV GX transceivers The programmable clock is controlled by a control bus connected to the MAX II EPM2210 device This can reduce the Stratix IV GX I O usage while enabling greater fun...

Page 88: ...agram T Th he e E EX XT T_ _P PL LL L_ _C CT TR RL L I IP P P Po or rt t D De es sc cr ri ip pt ti io on n This section describes the operation for the EXT_PLL_CTRL instruction hardware port Figure 5 2 shows the EXT_PLL_CTRL instruction block diagram connected to the MAX II EPM2210 device The EXT_PLL_CTRL controller module is defined by a host device the Stratix IV GX FPGA and a ...

Page 89: ..._PLL_CTRL instruction ports Table 5 1 EXT_PLL_CTRL Instruction Ports Port Name Direction Description osc_50 input System Clock 50MHz rstn input Synchronous Reset 0 Module Reset 1 Normal clk1_set_wr clk2_set_wr clk3_set_wr input Setting Output Frequency Value clk1_set_rd clk2_set_rd clk3_set_rd output Read Back Output Frequency Value conf_wr Input Start to Transfer Serial Data postive edge conf_rd ...

Page 90: ...C CT TR RL L I IP P T Ti im mi in ng g D Di ia ag gr ra am m In this reference design the output frequency is set to 62 5 75 and 100 MHz with the following timing diagrams illustrated below When the ext_pll_ctrl IP receives the conf_wr signal the user needs to define clk1_set_wr clk2_set_wr and clk3_set_wr to set the External Clock Generator When the ext_pll_ctrl IP receives the conf_rd signal it ...

Page 91: ... ve ef fo or rm m As BUTTON1 the trigger source defined by Terasic is pressed the conf_rd signal is on the rising edge the user settings are read back immediately once the conf_ready signal is on the falling edge as shown in Figure 5 4 As the transfer is complete the conf_ready returns back to original state at high level ...

Page 92: ... ou ur rc ce e C Co od de e Project directory TR4_EXT_PLL Bit stream used TR4_EXT_PLL sof Demonstration Batch File Demo Batch File Folder TR4_EXT_PLL demo_batch T Th he e d de em mo o b ba at tc ch h f fi il le e f fo ol ld de er rs s i in nc cl lu ud de e t th he e f fo ol ll lo ow wi in ng g f fi il le es s Batch File TR4_EXT_PLL bat FPGA Configuration File TR4_EXT_PLL sof ...

Page 93: ...ch provides a quick way to implement your own design utilizing the transceiver signals situated on the HSMC interface This design also helps you verify the transceiver signals functionality for ports A and E of the HSMC interface A total of 8 transceiver pairs on the HSMC Port A and port E each are tested H HS SM MC C P Po or rt t A A L Lo oo op pb ba ac ck k T Te es st t Demonstration Source Code...

Page 94: ...am TR4_HSME_LOOPBACK_TEST sof Demonstration Setup Check that Quartus II and Nios II are installed on your PC Insert the HSMC loopback daughter card onto the HSMC Port E as shown in Figure 5 5 Connect the USB Blaster cable to the TR4 board and host PC Install the USB Blaster driver if necessary Power on the TR4 board Program the TR4 using the TR4_HSME_LOOPBACK_TEST sof through Quartus II programmer...

Page 95: ...on the TR4 can be accessed We describe how the Altera s DDR3 SDRAM Controller with UniPHY IP is used to create a DDR3 SDRAM controller and how the Nios II processor is used to read and write the SDRAM for hardware verification The DDR3 SDRAM controller handles the complex aspects of using DDR3 SDRAM by initializing the memory devices managing SDRAM banks and keeping the devices refreshed at approp...

Page 96: ...controlled by a Nios II program First the Nios II program writes test patterns into the DDR3 filling it up to maximum capacity Then it calls a Nios II system function alt_dache_flush_all to make sure all data has been written Finally it reads data from DDR3 for data verification The program will show progress in JTAG Terminal when writing reading data to from the DDR3 When the verification process...

Page 97: ...Y_1G_QSYS Software D De em mo on ns st tr ra at ti io on n B Ba at tc ch h F Fi il le e Demo Batch File Folder TR4_DDR3_UniPHY_1G_QSYS demo_batch The demo batch file includes following files Batch File TR4_DDR3_UniPHY_1G_QSYS bat TR4_DDR3_UniPHY_1G_QSYS_bashrc FPGA Configuration File TR4_DDR3_UniPHY_1G_QSYS sof Nios II Program TR4_DDR3_UniPHY_1G_QSYS elf D De em mo on ns st tr ra at ti io on n S S...

Page 98: ...lly a prompt message will be displayed in nios2 terminal Press BUTTON3 BUTTON0 of the TR4 board to start the DDR3 verification process Press BUTTON0 to continue the test and Ctrl C to terminate the test The program will display the progress and result as shown in Figure 5 8 Figure 5 7 Insert the DDR3 SDRAM SODIMM for the DDR3 1G Demonstration ...

Page 99: ...a DDR3 SDRAM controller and modify the IP generated example top to test the entire space of DDR3 SDRAM This demonstration is a pure RTL project The required DDR3 SDRAM SODIMM module should be exactly 4 GB of DDR3 1066 F Fu un nc ct ti io on n B Bl lo oc ck k D Di ia ag gr ra am m Figure 5 9 shows the function block diagram of this demonstration The DDR3 controller is configured as a 4GB DDR3 1066 ...

Page 100: ...test will check the whole memory span of 4GB after finishing 4 1024 1024 loops A Al lt te er ra a D DD DR R3 3 S SD DR RA AM M C Co on nt tr ro ol ll le er r w wi it th h U Un ni iP PH HY Y To use Altera DDR3 controller users need to perform three major steps 1 Create correct pin assignment for DDR3 2 Setup correct parameters in DDR3 controller dialog 3 Execute TCL files generated by DDR3 IP under...

Page 101: ...ur PC Make sure DDR3 SDRAM SODIMM 4 GB is installed on your TR4 board as shown in Figure 5 10 Connect the USB Blaster cable to the TR4 board and host PC Install the USB Blaster driver if necessary Power on the TR4 board Execute the demo batch file TR4_DDR3_UniPHY_4G_RTL bat under the batch file folder TR4_DDR3_UniPHY_4G_RTL demo_batch Press BUTTON0 of the TR4 board to start the verification proces...

Page 102: ... terasic com March 30 2017 Figure 5 10 Insert DDR3 SDRAM SODIMM for the DDR3 4G Demonstration Table 5 3 LED Indicators NAME Description LED0 test complete LED1 test pass LED2 test fail LED3 local_init_done local_cal_success ...

Page 103: ... ev vi is si io on n H Hi is st to or ry y Date Version Changes 2011 12 29 First publication 2012 03 01 V1 1 Update PCA Card 2012 03 08 V1 2 Update PCIe driver 2013 09 10 V1 3 Update HSMC pin table 2014 2 10 V1 4 Swap pin assignment of hsmc table HSMC_RX_n0 HSMC_RX_p0 2014 3 18 V1 5 Modify table2 7 and HSMC feature 2015 01 07 V1 6 Update FPGA embedded ram size 2015 06 03 V1 7 Modify table 7 6 to c...

Page 104: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Terasic P0107 P0109 ...

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