- 20 -
HDMI-FMC_User_Manual
August 6, 2019
1 – active low
(leading edge
falls)
rises)
1 – active low
(leading edge
falls)
DE_ADJ#
enables detection circuits to locate the position of VSYNC relative to HSYNC and only include HSYNC
edges that are greater than three-fourths of a line from VSYNC in the line count for DE_TOP. Clearing this bit
enables the function and is recommended for normal operation. Setting it high disables VSYNC adjustments and is
not a recommended setting.
F2VADJ
adjusts the VBIT_TO_VSYNC value during field 2 of an interlace frame;
F2VOFST
sets the direction of
adjustment (increment or decrement by 1).
Invert Field Polarity.
The Invert Field Polarity bit is used when the 656 Flag Bit is opposite the standard polarity
for Field1 and Field2. Inverting polarity causes the sync extraction to format HSYNC and VSYNC properly based
on the Fbit. In embedded sync mode, the transmitter does not detect even from odd field, except based on the setting
of the F-bit. With explicit syncs, the transmitter encodes HSYNC and VSYNC across the HDMI/TMDS link without
regard for field sequence.
◼
I2S Input Configuration Register
Configuring Audio Using I
2
S
The I2S audio subsystem selection is made by TPI control.
I2S Initialization and Operation
The transmitter requires the following initialization for I2S applications.
1. Ensure that a valid I2S audio stream is coming into the transmitter.
2. Select I2S input mode using TPI 0x26[7:6], with Mute enabled (bit [4] = 1).
3. Write register TPI 0x20 to select the general incoming SD format.
4. Write register TPI 0x1F up to four times, to program each of the SD inputs.
5. Program register TPI 0x27[5:3] with the correct audio rate.
6. Program registers TPI 0x21–0x25 with the correct header information for the stream that will be
sent over HDMI.
7. Write registers TPI 0xBF–0xCD with the appropriate Audio InfoFrame information.
8. Set the audio packet header layout indicator to 2-channel or multi-channel mode as needed using
the sequence.
described below. Note that Audio InfoFrame byte 1 must also have this same setting.
9. Again write register TPI 0x26 with I2S selected, this time with Mute disabled (bit [4] = 0).
Summary of Contents for HDMI-FMC
Page 1: ......
