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HDMI-FMC_User_Manual
August 6, 2019
There are individual components processing the video and audio input data. In the video data input
and conversion block, the bus configurations support most standardized video input formats as well
as other widely used non-standard formats. After configuration and processing, the clock, data, and
sync information are combined into a complete set of signals required for further processing as
follows. The upsampler and downsampler block convert the 4:2:2 sampled video to 4:4:4 and 4:4:4
sampled video to 4:2:2 seperately. The two color space converters (CSCs, convert YCbCr to RGB and
RGB to YCbCr) are available to interface to the many video formats supplied by A/V processors and
provide full DVI backward compatibility. RGB range expression block scales the input color range
from limited-range into full-range and RGB/YCbCr range compression compresses full-range data
into limited-range data for each video channel. The clipping and dither function are also employed in
the transmitter. The audio capture block supports I2S, Direct Stream Digital, and S/PDIF audio input
formats. The appropriate registers must be configured to describe the audio format provided to the
SiI9136-3 transmitter.
There is a Transition-minimized differential signaling(TMDS) transmitter for the output. The TMDS
digital core performs 8-to-10-bit TMDS encoding and is then sent over three TMDS data and a
TMDS clock differential lines. All of the above operations can be controlled by the configuration
registers which can be accessed via the I2C interface.
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Register Table for HDMI TX Chip
◼
Internal (Indexed) Registers
Underlying the TPI register set is a broader and more complex internal register set that is normally
hidden from direct access. This register set includes the legacy registers that were available in older
programming methodologies, but also some additional registers that are used primarily during chip
development and testing.
From time to time, situations arise that require customer software to manually access these internal
registers. Therefore, a mechanism is provided for accessing single bytes. Where defined, Internal
Registers are accessed as noted below.
1. Set Page
2. Select Indexed Offset within Page
3. Obtain Read/Write Register Access
0xBC
0xBD
0xBE
Summary of Contents for HDMI-FMC
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