Clock Configuration and Other Switch Settings
SW2
: The source for the reference clock used by the analyzer to record PCI Express traffic is configurable according to
below table for SW2. Make sure clock source in Recording Options in the PCIe Protocol Analysis application is set to
External.
Note:
Factory default is host clock: SW2.1 = ON, SW2.2 = ON, SW2.3 = ON, SW2.4 = ON
Note:
Other switch configurations (other than those shown in the table above) are invalid.
Note:
External input clocks can be HCSL, LVPECL, LVDS or any single ended standard input voltage amplitude not to
exceed 800mV.
SW3:
A pushbutton SW3 is used to turn off the terminations and remove all loads on the unused interposer receivers
depending on the maximum number of lanes to be analyzed. Press the pushbutton switch (SW3) to move to the next active
width as indicated by the LEDs (next to the switch on the interposer.
DUT Power LED Status on Interposer
SW4:
This switch connects the DUT power indication LEDs to the bus power. In some systems with Hot-Plug management
the Power Indication LEDs on the interposer may prevent the host system from turning ON bus power to the device, if this
happens disconnect the LEDs using SW4 to allow proper bus power operation.
SW2: Clock Source Control
SW2.1
SW2.2
Reference Clock Source
for Downstream Analysis
SW2.3
SW2.4
Reference Clock Source
for Upstream Analysis
ON
ON
Host System PCIe Slot
Connector
ON
ON
Host System PCIe Slot
Connector
OFF
ON
US_CLK from MMCX connector
OFF
ON
US_CLK from MMCX connector
ON
OFF
DS_CLK from MMCX connector
ON
OFF
DS_CLK from MMCX connector
OFF
OFF
No clocks supplied to analyzer
OFF
OFF
No clocks supplied to analyzer
SW4: Link Width Select LED
ON
LED Connected (Default)
OFF
LED Disconnected
SW3 Active Link Width Select
6
SW4 DUT Power LED
