Enabling CrossSync PHY Capability
Use the following procedure to enable CrossSync PHY for your the interposer:
1.
Locate any miscellaneous signals to be probed.
Top View
2.
Locate the PCIe Express pairs probe points, as located on the left and right sides of the interposer.
Left Side View
Right Side View
Buffered Refclk
Copy (
UMC
)
Pin Header for
Sideband Signals
3.3V Rail Voltage
(UMC)
3.3V Rail Current
shunt (1V=1A
)
(UMC)
Passive Probe
Ground
s
Upstream Signal Probe
Points (Optional)
Downstream Signal
Probe Points(Optional)
