SDI Eye and Jitter Measurements
How-to Guide
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Figure 13c shows a jitter meter value of 0.16UI with a 1kHz high pass filter selected and Figure 13d shows
a jitter meter value of 0.09UI with a 100kHz high pass filter applied (Alignment).
In this case the jitter value has decreased as the HPF value has been increased and there is minimal jitter
within the Alignment HPF that means the PLL will be able to track this SDI signal to maintain the clock and
data of the signal.
Figure 13c.
Jitter display with 1kHz HPF.
Figure 13d.
Jitter display with 100kHz HPF.
There are certain circumstances when jitter is higher as the HPF is increased:
If there is a larger amount of jitter present when the 100kHz filter is selected then the PLL may have
problems tracking these changes and cause a disturbance to the clock and data that will produce errors
in the signal.
Another instance is if a jitter frequency is present at the passband of the high pass filter. The HP Filter
has a specific rolloff and jitter frequency present within the roll off bandwidth can be differentiated by the
filter and produce an increase in jitter value around this passband.
Jitter within the SDI signal arises from processing of active devices and can be due to signals that affect the
device’s phase lock loop such as noise from a power supply at 60Hz or a noisy video reference that is used to
genlock the device and affects the clock of the device. An MPEG decoder can also introduce jitter at the SDI
output if the program clock reference is not within limits and causes a disturbance to the clock within the
device.
