Tektronix TLA500 Series, Technical Reference

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Speci fi cations
Table 3: TLA5000 timing latencies (cont.)
Characteristic Description
LA Probe Tip to External System Trigger Out 5 6 778 ns + SMPL
OR function 772 ns + SMPL LA Probe Tip to External
Signal Out via Signal 3,
4
5 6
AND function 772 ns + SMPL
normal function 772 ns + SMPL
System Trigger and
External Signal Output
Latencies
(Typical)
LA Probe Tip to External
Signal Out via Signal 1, 2
4 5 6
inverted logic on backplane 774 ns + SMPL
1
All system trigger and external signal input latencies are measured from a falling-edge transition (active true low) with signals measured in the wired-OR
con fi guration.
2 In the Waveform window, triggers are always marked immediately except when delayed to the fi rst sample. In the Listing window, triggers are always
marked on the next sample period following their occurrence.
3
CLK represents the time to the next master clock at the destination. In Normal clocking, this represents the delta time to the next sample clock. In External
clocking, this represents the time to the next master clock generated by the setup of the clocking state machine and the supplied SUT clocks and quali fi cation date.
4
Signals 1 and 2 (ECLTRG 0, 1) are limited to a "broadcast" mode of operation, where only one source is allowed to drive the signal node at any one time.
That single source can be used to drive any combination of destinations.
5 SMPL represents the time from the event to the next valid data sample at the probe tip input. In the Normal Internal clock mode, this represents the delta time to
the next sample clock. In the MagniVu Internal clock mode, this represents 125 ps. In the External clock mode, this represents the time to the next master clock
generated by the setup of the clocking state machine, the SUT-supplied clocks, and the quali fi cation data.
6 All signal output latencies are validated to the rising edge of an active (true) high output.
Table 4: TLA5000 external signal interface
Characteristic Description
TTL compatible input via rear panel mounted BNC connectors
Input destination System trigger
Input levels
V
IH
V
IL
TTL compatible input
≥ 2.0 V
≤ 0.8 V
Input mode Falling edge sensitive, latched (active low)
Minimum pulse width 12 ns
Active period Accepts system triggers during valid acquisition periods via real-time
gating, resets system trigger input latch between valid acquisition periods.
System trigger input
Maximum input voltage 0 to +5 V peak
TTL compatible input via rear panel mounted BNC connectors
Input destination
Signal 1, 2, 3, 4
Input levels
V
IH
V
IL
TTL compatible input
≥ 2.0 V
≤ 0.8 V
Input mode Active (true) low, level sensitive
Signal 1, 2 Signal 3, 4 Input bandwidth 1
50 MHz square wave minimum 10 MHz square wave minimum
Active period Accepts signals during valid acquisition periods via real-time gating.
External signal input
Maximum input voltage 0 to +5 V peak
6 TLA5000 Series Product Speci fi cations & Performance Veri fi cation