Theory of Operation
2-6
MTX100A MPEG Recorder & Player Service Manual
A110 Universal Parallel/Serial Interface Module (Option 02)
The A110 Universal Parallel/Serial Interface module consists of the following
blocks:
The local bus interface communicates with the A12 Main board. There are two
sets of 16-bit signal lines for Rx and Tx: 8-bit data lines for single-end connec-
tion, 4-bit control lines for single-end connection, and 4-bit control lines for
differential connection. These lines are connected to the A12 Main board
individually.
The FPGA consists of an 8-bit-to-1-bit shift register for parallel to serial
conversion, a 1-bit-to-8-bit shift register for serial to parallel conversion, and a
PCI interface. The shift registers are not used in the parallel data input/output
mode. There is a 32-bit resistor in the PCI interface. It controls the board
operation.
The pin drivers convert output signals from the FPGA into the signals with the
selected level. Two drivers per 1 bit are always working: two drivers are used for
differential mode and one driver is used for single-end mode.
The receivers use two comparators per 1 bit. One is used to receive a single-end
signal and the other is used to receive a differential signal. One of the comparator
is always disabled in operation and is in hold mode.
The D/A converter is used to set the amplitude and offset of the output signal. It
also sets the threshold voltage of the comparator for single-end receiving.
The regulator supplies power for internal circuitry in the FPGA.
A140 IEEE 1394/ASI Interface Module (Option 05)
Two operational modes are available to output data from the ASI interface:
Packet mode and Byte mode.
Difference between Packet and Byte Modes.
Data rate of the ASI interface is up to
216 Mbps, and data with rates lower than 216 Mbps is transmitted intermittently.
The Data Valid signal, which indicates the location in which the data exists, is
also sent together with the data; it is possible to reconfigure the received data as
a serial data string from the intermittently transmitted data.
Local Bus Interface
FPGA
Pin Drivers
Receivers
D/A Converter
2.5 V Regulator
Packet Controller
Summary of Contents for MTX100A
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Page 14: ...Service Safety Summary x MTX100A MPEG Recorder Player Service Manual ...
Page 16: ...Environmental Considerations xii MTX100A MPEG Recorder Player Service Manual ...
Page 21: ...Specifications ...
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Page 24: ...Product Overview 1 2 MTX100A MPEG Recorder Player Service Manual ...
Page 39: ...Theory of Operation ...
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Page 51: ...Performance Verification ...
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Page 105: ...Maintenance ...
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Page 140: ...Removal and Installation Procedures 4 34 MTX100A MPEG Recorder Player Service Manual ...
Page 152: ...Troubleshooting 4 46 MTX100A MPEG Recorder Player Service Manual ...
Page 156: ...Using the Recovery Discs 4 50 MTX100A MPEG Recorder Player Service Manual ...
Page 157: ...Options ...
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Page 160: ...Options 5 2 MTX100A MPEG Recorder Player Service Manual ...
Page 161: ...Diagrams ...
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Page 173: ...Replaceable Parts List ...
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Page 190: ...Replaceable Parts List 7 16 MTX100A MPEG Recorder Player Service Manual ...