Theory of Operation
MTX100A MPEG Recorder & Player Service Manual
2-9
Sync Detector 2.
This circuit produces the sync location information to be
delivered to the Partial TS Control 2 circuit. The circuit is compatible only with
the packet size of 188 bytes/packet. Should a packet having a size other than 188
bytes/packet be input even if Partial TS processing is specified, the circuit stops
the output to the A12 board.
A170 SMPTE310M/ASI/PSI Interface Module (Option 07)
The SMPTE310M format supports data with a bit rate of 8-VSB (19.39 Mbps).
Because the SMPTE310M uses Biphase-mark coding, a clock with twice the
data bit rate (40 MHz) is required for decoding and encoding processes. The
receiver passes the received data signal through a delay line to generate a clock
signal with twice the data bit rate from the received data signal. The transmitter
receives the clock signal with twice the data bit rate from A12 board for data
encoding. Because this optional board is unable to recognize the difference of
data bit rates, the current data bit rate must be specified from the application.
Two operational modes are available to output data from the ASI interface:
Packet mode and Byte mode.
Difference between Packet and Byte Modes.
Data rate of the ASI interface is up to
216 Mbps, and the data with rates lower than 216 Mbps are transmitted
intermittently. The Data Valid signal, which indicates the location in which the
data exists, is also sent together with the data. It is possible to reconfigure the
received data as a serial data string from the intermittently transmitted data.
When the data rate from the MTX100A storage (hard disk or RAM) is lower
than 216Mbps, it is possible to select whether to sparsely output all the data or to
output the data on a packet-by-packet basis as the ASI output. The first mode in
which the data is sparsely output is called Byte mode, and the second mode in
which the data is output on a packet-by-packet basis is called Packet mode. In
Byte mode, the data sent from the A12 board are output as they are. In Packet
mode, data processing is required.
Packet Mode Operation.
The FIFO shift register is used to output the data on a
packet-by-packet basis. This FIFO has 9 bits of width, and its depth is
512 stages. The content of 9-bit width is 8 bits for data, and 1 bit for Sync Bit.
The Sync bit indicates the location of sync pattern (47h) in the data.
The data sent from the A12 board is fed to the FIFO. The FIFO output port
searches for a Sync Bit. When a Sync Bit is detected, data output from the FIFO
is stopped, and the data that follows the Sync Bit is stored in the FIFO.
SMPTE310M
Packet Controller
Summary of Contents for MTX100A
Page 4: ......
Page 14: ...Service Safety Summary x MTX100A MPEG Recorder Player Service Manual ...
Page 16: ...Environmental Considerations xii MTX100A MPEG Recorder Player Service Manual ...
Page 21: ...Specifications ...
Page 22: ......
Page 24: ...Product Overview 1 2 MTX100A MPEG Recorder Player Service Manual ...
Page 39: ...Theory of Operation ...
Page 40: ......
Page 51: ...Performance Verification ...
Page 52: ......
Page 105: ...Maintenance ...
Page 106: ......
Page 140: ...Removal and Installation Procedures 4 34 MTX100A MPEG Recorder Player Service Manual ...
Page 152: ...Troubleshooting 4 46 MTX100A MPEG Recorder Player Service Manual ...
Page 156: ...Using the Recovery Discs 4 50 MTX100A MPEG Recorder Player Service Manual ...
Page 157: ...Options ...
Page 158: ......
Page 160: ...Options 5 2 MTX100A MPEG Recorder Player Service Manual ...
Page 161: ...Diagrams ...
Page 162: ......
Page 164: ...Diagrams 6 2 MTX100A MPEG Recorder Player Service Manual ...
Page 166: ...6 4 MTX100A MPEG Recorder Player Service Manual ...
Page 168: ...6 6 MTX100A MPEG Recorder Player Service Manual ...
Page 173: ...Replaceable Parts List ...
Page 174: ......
Page 190: ...Replaceable Parts List 7 16 MTX100A MPEG Recorder Player Service Manual ...