Theory of Operation
MTX100A MPEG Recorder & Player Service Manual
2-5
Two operational modes are available to output data from the ASI interface:
Packet mode and Byte mode.
Difference between Packet and Byte Modes.
Data rate of the ASI interface is up to
216 Mbps, and the data with rates lower than 216 Mbps are transmitted
intermittently. The Data Valid signal, which indicates the location in which the
data exists, is also sent together with the data, it is possible to reconfigure the
received data as a serial data string from the intermittently transmitted data.
When the data rate from the MTX100A storage (hard disk or RAM) is lower
than 216Mbps, it is possible to select whether to sparsely output all the data or to
output the data on a packet-by-packet basis as the ASI output. The first mode in
which the data is sparsely output is called Byte mode, and the second mode in
which the data is output on a packet-by-packet basis is called Packet mode. In
Byte mode, the data sent from the A12 board are output as they are. In Packet
mode, data processing is required.
Packet Mode Operation.
The FIFO shift register is used to output the data on a
packet-by-packet basis. This FIFO has 9 bits of width, and its depth is
512 stages. The content of 9-bit width is 8 bits for data, and 1 bit for Sync Bit.
The Sync bit indicates the location of sync pattern (47h) in the data.
The data sent from the A12 board is fed to the FIFO. The FIFO output port
searches for a Sync Bit. When a Sync Bit is detected, data output from the FIFO
is stopped, and the data that follows the Sync Bit is stored in the FIFO.
The FIFO input port also searches for a Sync Bit. When the port detects a Sync
Bit in the next packet, it sends the detection to the read-out controller at the
FIFO output port. When the FIFO output port receives the Sync Bit detection
signal from the input port, the output port reads out the signals until the next
packet Sync Bit is detected. The data rate of FIFO input port is equal to the data
transfer rate of MTX100A, and that of output port is 216 Mbps (with the clock
of 27 MHz), which is used for the ASI output.
The HOTLink transmitter converts parallel signals from the FIFO to a serial
signal. The converted signal is output to the BNC connectors through the cable
drivers.
The signal applied to the BNC connector is equalized by the cable equalizer, and
is converted to parallel signals by the HOTLink receiver. In addition, the
equalized signal is applied to the cable driver, and is output to the ASI through
output.
The regulator supplies power for internal circuitry in the FPGA.
Packet Controller
HOTLink transmitter and
Cable Drivers
Cable Equalizer and
HOTLink Receiver
2.5 V Regulator
Summary of Contents for MTX100A
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Page 14: ...Service Safety Summary x MTX100A MPEG Recorder Player Service Manual ...
Page 16: ...Environmental Considerations xii MTX100A MPEG Recorder Player Service Manual ...
Page 21: ...Specifications ...
Page 22: ......
Page 24: ...Product Overview 1 2 MTX100A MPEG Recorder Player Service Manual ...
Page 39: ...Theory of Operation ...
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Page 51: ...Performance Verification ...
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Page 105: ...Maintenance ...
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Page 140: ...Removal and Installation Procedures 4 34 MTX100A MPEG Recorder Player Service Manual ...
Page 152: ...Troubleshooting 4 46 MTX100A MPEG Recorder Player Service Manual ...
Page 156: ...Using the Recovery Discs 4 50 MTX100A MPEG Recorder Player Service Manual ...
Page 157: ...Options ...
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Page 160: ...Options 5 2 MTX100A MPEG Recorder Player Service Manual ...
Page 161: ...Diagrams ...
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Page 164: ...Diagrams 6 2 MTX100A MPEG Recorder Player Service Manual ...
Page 166: ...6 4 MTX100A MPEG Recorder Player Service Manual ...
Page 168: ...6 6 MTX100A MPEG Recorder Player Service Manual ...
Page 173: ...Replaceable Parts List ...
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Page 190: ...Replaceable Parts List 7 16 MTX100A MPEG Recorder Player Service Manual ...