Theory
of
Operation-DC
502
1 MHz clock
RESET
Forced by RESET
RBI, pin 5
U270
Fig. 2-2.
Multiplexing circuit
ladder diagram showing timing with an all-zero display.
input
of OR
gate
U245B via these NAND gates,
setting
U263B
to
the non-blank state at the appropriate time. In
the
case
where
the counter overflows,
the HI output from
U245A
is
applied
to U245B, setting U263B to the
non-blank
state.
When
the front-panel RESET button
is pushed, RESET
goes LO,
overriding
the output of
U263B, applying the
non-blank
and lamp-test
functions to the decoder. This
causes
all
seven
segments in the display
LED to be turned
on.
POWER
SUPPLIES
AND INPUT/OUTPUT LINES
Regulated Power
Supplies
The
DC 502 operating power is obtained from the power
module
mainframe and then
electronically
regulated to
provide
stable
supplies of +15 volts, +5 volts, —5.2 volts,
and
—10 volts. The +15-volt supply, whose active device is
U300,
provides the reference for the remaining supplies. Its
output
is set to
+15 V by adjustment of R305.
Integrated circuit
U320 regulates the
+5-volt supply, and
transistors Q330
and Q340 regulate the —5.2-volt and
—
10-volt
supplies
respectively.
The series-pass transistors
for
these supplies
are located in the mainframe, where they
can
provide the
proper heat dissipation.
INT SCAN DISABLE:
A LO applied to this line
disables
the internal
scan clock.
EXT
SCAN: Provides input for
an external scan clock.
INT SCAN CLOCK OUT: Provides output
for the
internal scan clock.
TS0: A
LO is present on this output line in the
TS
q
state.
Input/Output
Lines
The
following
inputs and outputs are
available
via the
plug-in
connector to
external equipment. See Fig. 1-3, also.
DATA
GOOD:
A
HI
is present on this output line when
a
new reading is being transferred into the
storage-register
latches.
2-5
Summary of Contents for DC 502
Page 4: ...DC 502...
Page 24: ...39 39 Relocated on back of board SN B070000 REV MAY 1974...
Page 33: ...FIG 1 EXPLODED...
