Tektronix DC 502, Instruction Manual

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Theory of Operation — DC 502
described in the time base and control circuit. When the
LATCH input goes HI, the logic levels at the data inputs are
transferred to the associated BCD bit output to be scanned
by the multiplexing circuit.
Overflow Register
When the decade counters have counted to 9,999,999,
the counters are full. At the next count, the 23 output of
U240 goes LO, providing a toggle input to U241B. When
this occurs, a LO is transferred from pin 10 to pin 8 of
U241B, then when the LATCH pulse ends (goes LO),
U241A is toggled and the LO is transferred to pin 13. When
pin 13 of U241A goes LO, CR241 and DS242 conduct.
DS242 is an LED, and in its conduction state gives a
front-panel OVERFLOW indication.
In the Manual counting mode, OVERFLOW indication is
achieved via Q242 and CR244. The emitter of Q242 is
grounded by a switch closure, then when pin 9 of U241B
goes HI on the first overflow count, Q242, CR244, and
DS242 turn on.
U241 is reset by the CLEAR pulse. To prevent leading­
zero suppression during the overflow condition, the display­
controlling circuits
are notified via U245A that the count is
in excess of that displayed by the LED readout.
DECODE AND DISPLAY MULTIPLEX
Scan Clock
The scan rate of the multiplexing circuit is determined
by the scan clock. The scan clock is composed of U260B
and U260D, which operate as a free-running multivibrator
at an approximate 2-kilohertz rate. The scan-clock output is
passed through NOR gate U260A, which can also accept an
externally applied scan-clock signal. Other input/output
lines provide internal scan-clock disable and internal scan­
clock output. The scan clock drives an eight-state counter
and a storage register for zero suppression.
÷ 8 Counter and Time-Slot Decoder
The divide-by-eight counter is made up of U262B,
U263A, and U262A, which are three halves of SN7474
type D flip-flops. The output of this counter drives U265,
an SN74145 BCD-to-decimal decoder. U265 provides eight
output lines (designated TS0 through TS7
in the schematics
and in Fig. 2-2) to simultaneously enable the output of
each counter latch and its corresponding display LED
sequentially. For example, when the TS1 line goes LO,
Q280 is turned on to supply anode voltage to DS280 at the
same time inverter U267C applies a HI to pin 6 of latch
U256, enabling its output. Operation in a time sequence
allows the latches to share a common set of output lines.
Seven-Segment Decoder and Display LED's
U270 is a BCD-to-seven decoder. It accepts the BCD
output of the latches, then supplies current to the
appropriate cathodes of the enabled LED to display the
correct number. The display LED's are DS280 through
DS286. When looking at the front panel of the DC 502,
DS280 controls the numerical digit displayed at the far left
(10 6 ), DS281 controls the second (105),etc. Each LED has
seven segments, arranged so that a combination of lighted
segments forms a number. When all of the segments are
lighted, an “8" is formed.
Leading Zero Suppression
Decoder driver U270 also has a zero-blanking feature
which allows suppression of the zeroes leading the most
significant digit (MSD) in the display. At TS0, a LO is
applied to the direct-clear input of U263B, the zero­
suppression storage register. This sets U263B to the
zero-suppress state (HI at pin 8), allowing the Ripple-
Blanking Input (RBI, pin 5) of
U270 to be LO. When the
output of U265 advances to the next time slot (TS1), the
RBI of U270 remains LO for a few nanoseconds due to
propagation delays, which allows the first digit to arrive
from the latches while RBI is LO. If this first digit being
decoded is a zero, the output to the display LED will be
inhibited and the Ripple Blanking Output (pin 4) will be
LO. If the digit is not a zero, the outputs are enabled and
RBO goes HI. The.RBO is applied to the D input (pin 12)
of U263B and is transferred to the output when the next
scan-clock HI-to-LO transition occurs. Thus, if the first
digit is a zero, pin 5 of U270 is held LO, inhibiting the
output until the first non-zero digit comes through the
decoder. When the first non-zero digit arrives, the outputs
of U270 are enabled and the digit is displayed. Also, the
RBO output at pin 4 is set HI, removing the RBI from pin 5
and allowing all succeeding digits to be displayed through
the TS7 sequence.
When the scan gets past the decimal point in the display,
or if the display overflows, any zeroes arriving at the
decoder should be displayed.
This is achieved as follows:
TS5 is inverted by U267E and applied through OR gate
U245B as a LO at the direct-set input of U263B. This holds
pin 5 of U270 HI, preventing zero-blanking during the TS5,
TS 6, and TS7 time slots. The location of the decimal point
in the display is determined by the MEASUREMENT
INTERVAL switch.
The proper information is applied via
the closed contacts of the switch to either NAND gate
U246A or U246B. Then either TS3 or TS4 is enabled to the
2-4