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TechNexion EDM1-IMX6PLUS Hardware Manual Download Page 13

EDM1-IMX6PLUS HARDWARE MANUAL 

– VER 1.00 – NOV 16 2016 

Page 

13

 of 

83

 

1.6. Component Location 

 

Figure 4 - EDM1-IMX6PLUS Top view 

 

 

Item 

Description 

Item 

Description 

1 

NXP i.MX6 Processor 

6 

MIPI Camera / Display Connector 

2 

MMPF0100 Power Management IC 

7 

WiFi / BT Module 

3 

NAND Flash / eMMC (co-layout) 

8 

Antenna Connector 

4 

JTAG Interface 

9 

EDM Type 1 Connector 

5 

Memory IC (2) 

 

 

 

 

Figure 5 - EDM1-IMX6PLUS Bottom view 

 

 

Item 

Description 

Item 

Description 

1 

Atheros AR8035 Gigabit Ethernet PHY 

2 

Memory IC (2) 

 
 

 

1 

2 

3 

4 

7 

5 

6 

8 

1 

2 

2 

9 

5 

Summary of Contents for EDM1-IMX6PLUS

Page 1: ...EDM1 IMX6PLUS VER 1 00 November 16 2016 ...

Page 2: ...EDM1 IMX6PLUS HARDWARE MANUAL VER 1 00 NOV 16 2016 Page 2 of 83 REVISION HISTORY Revision Date Originator Notes 1 00 November 16 2016 TechNexion Initial Public Release ...

Page 3: ...eMMC Storage 20 2 4 NAND Flash Storage 22 2 5 WiFi Bluetooth SIP Module 24 2 6 Atheros AR8035 Gigabit LAN 28 2 6 1 Gigabit Ethernet Magnetics 30 2 7 MIPI Camera and Display Connector 32 2 7 1 MIPI Camera 32 2 7 2 MIPI Display 33 2 8 JTAG Connector 35 3 EDM Type 1 Connector Interfaces 36 3 1 Gigabit Ethernet 36 3 2 LVDS Interface 37 3 3 HDMI High Definition Multi Media Interface 39 3 4 Digital Disp...

Page 4: ...ring and Boot Control 60 3 17 Input Power Requirements 62 3 17 1 Power Management Signals 62 3 17 2 Power Sequencing for AT based configurations 63 3 17 3 Power Sequencing for ATX based configurations 64 3 17 4 EDM1 IMX6PLUS Power Option without Carrier Board 65 4 EDM Connector Pin Assignment 66 5 EDM Pinmux Overview 77 6 Ordering information Evaluation Components and Accessories 80 6 1 Product Or...

Page 5: ...gnal Description 44 Table 20 PCI Express Signal Description 45 Table 21 Serial ATA Signal Description 46 Table 22 USB Host Signal Description 48 Table 23 USB OTG Signal Description 48 Table 24 SDIO MMC Interface Signal Description 49 Table 25 GPMC Local Bus Signal Description 51 Table 26 Primary CAN Bus Signal Description 52 Table 27 Secondary CAN Bus Signal Description 52 Table 28 Primary UART Si...

Page 6: ...ssor Scalability Overview Solo Duallite Dual Quad QuadPlus 15 Figure 8 eMMC Schematics 21 Figure 9 NAND IC Schematics 23 Figure 10 EDM1 IMX6PLUS Antenna u FL Connector Location 24 Figure 11 WiFi BT Schematics 27 Figure 12 Gigabit Ethernet Schematics 31 Figure 13 EDM1 FAIRY with EDM MNF BOOT 61 Figure 14 Input Power sequence for AT based configurations 63 Figure 15 Input Power sequence for ATX base...

Page 7: ...ffective and with low power consumption The EDM1 IMX6PLUS System on Module is typically being used as building blocks for portable and stationary embedded systems The core CPU and support circuits including DRAM booth flash power sequencing CPU power supplies Gigabit Ethernet and display interfaces are concentrated on the module The modules are used with application specific carrier boards that im...

Page 8: ...n Unauthorized modifications or attachments could damage the device and may violate regulations governing radio devices These suggestions apply equally to your device battery charger or any enhancement If any device is not working properly take it to the nearest authorized service facility for service Regulatory information Disposal of Waste Equipment by Users in Private Household in the European ...

Page 9: ... encouraged to try to correct the interference by one or more of the following measures Reorient or relocate the receiving antenna Increase the separation between the equipment and receiver Connect the equipment to an outlet on a different circuit from that to which the receiver is connected Consult the dealer or an experienced radio TV technician for help WARNING To reduce the possibility of heat...

Page 10: ...EDM1 IMX6PLUS HARDWARE MANUAL VER 1 00 NOV 16 2016 Page 10 of 83 1 3 Block Diagram Figure 1 EDM1 IMX6PLUS Block Diagram ...

Page 11: ...bit HDMI 1 HDMI ver 1 4 compatible TTL Display 1 TTL 18 24 bit Display PCIe 1 Lane PCIe 2 0 SATA 1 SATA II USB Host 1 USB 2 0 Host port USB OTG 1 USB 2 0 OTG port possible to use in Host mode GPMC 8 bit localbus interface with 4 chip selects I2S 2 Independent I2S interfaces SPDIF 1 S P DIF interface CAN Bus 2 FlexCAN CAN 2 0B protocol compliant interfaces UART 2 UART 4 wire SDIO 1 SDIO interface 4...

Page 12: ... Type 1 Compact Form Factor System on Module and follows the EDM Standard Specifications in regards of dimensions and mounting options 2D and 3D files can be obtained from the www technexion com homepage For additional details please refer to the EDM Standard Specifications Figure 3 EDM1 IMX6PLUS Dimensional Drawing ...

Page 13: ...on 1 NXP i MX6 Processor 6 MIPI Camera Display Connector 2 MMPF0100 Power Management IC 7 WiFi BT Module 3 NAND Flash eMMC co layout 8 Antenna Connector 4 JTAG Interface 9 EDM Type 1 Connector 5 Memory IC 2 Figure 5 EDM1 IMX6PLUS Bottom view Item Description Item Description 1 Atheros AR8035 Gigabit Ethernet PHY 2 Memory IC 2 1 2 3 4 7 5 6 8 1 2 2 9 5 ...

Page 14: ...chdog o Cortex A9 NEON MPE Media Processing Engine Co processor Level 2 Cache Unified instruction and data up to 1 MByte General Interrupt Controller GIC with 128 interrupt support Global Timer Snoop Control Unit SCU NEON MPE coprocessor o SIMD Media Processing Architecture o NEON register file with 32x64 bit general purpose registers o NEON Integer execute pipeline ALU Shift MAC o NEON dual singl...

Page 15: ...EDM1 IMX6PLUS HARDWARE MANUAL VER 1 00 NOV 16 2016 Page 15 of 83 Figure 7 NXP i MX6 Processor Scalability Overview Solo Duallite Dual Quad QuadPlus ...

Page 16: ...ne It helps in maximizing system performance by off loading the various cores in dynamic data routing It has the following features Powered by a 16 bit Instruction Set micro RISC engine Multi channel DMA supporting up to 32 time division multiplexed DMA channels 48 events with total flexibility to trigger any combination of channels Memory accesses including linear FIFO and 2D addressing Shared pe...

Page 17: ... full HD 1920x1088 30fps GPU2Dv2 Hardware acceleration of 2D graphics Bit BLT and Stretch BLT Based on the Vivante GC320 IP core GPUVG An OpenVG 1 1 Graphics Processing Unit providing hardware acceleration of vector graphics Based on the Vivante GC355 IP core Additionally the EDM1 IMX6PLUS incorporates the following 3D GPU engine The EDM1 IMX6PLUS featuring an i MX6 Solo or Duallite processor GPU3...

Page 18: ...d by the components on the EDM1 IMX6PLUS module Table 2 PMIC Signal Description PMIC PIN i MX6 BALL PAD NAME Signal V I O Description 53 R2 GPIO_05 I2C3_SCL 3V3 I O I2C bus clock line 54 R4 GPIO_16 I2C3_SDA 3V3 I O I2C bus data line 56 D11 PMIC_ON_REQ PMIC_ON_REQ 3V3 I PMIC Power ON OFF Input from processor 1 U20 PMIC_INT_B PMIC_INT_B 3V3 I PMIC Interupt Signal 3 C11 POR_B POR_B 3V3 I PMIC Reset S...

Page 19: ...nous DRAM in either a single 32 bit or a dual 64 bit channel configuration The following memory chips have been validated and tested on the EDM1 IMX6PLUS System on Module SKHynix Samsung ISSI Micron NOTE The i MX6 Solo only support single 32 bit channel configuration For more information please contact your TechNexion sales representative ...

Page 20: ...mation please contact your TechNexion sales representative Table 3 eMMC Signal Description i MX6 BALL PAD NAME Signal V I O Description E14 SD3_DAT0 eMMC_DATA0 3V3 I O MMC SDIO Data bit 0 F14 SD3_DAT1 eMMC_DATA1 3V3 I O MMC SDIO Data bit 1 A15 SD3_DAT2 eMMC_DATA2 3V3 I O MMC SDIO Data bit 2 B15 SD3_DAT3 eMMC_DATA3 3V3 I O MMC SDIO Data bit 3 D13 SD3_DAT4 eMMC_DATA4 3V3 I O MMC SDIO Data bit 4 C13 ...

Page 21: ...EDM1 IMX6PLUS HARDWARE MANUAL VER 1 00 NOV 16 2016 Page 21 of 83 Figure 8 eMMC Schematics ...

Page 22: ...A02 3V3 I O GPMC data bit 2 D17 NANDF_D3 NAND_DATA03 3V3 I O GPMC data bit 3 A19 NANDF_D4 NAND_DATA04 3V3 I O GPMC data bit 4 B18 NANDF_D5 NAND_DATA05 3V3 I O GPMC data bit 5 E17 NANDF_D6 NAND_DATA06 3V3 I O GPMC data bit 6 C18 NANDF_D7 NAND_DATA07 3V3 I O GPMC data bit 7 B16 NANDF_RB0 NAND_READY_B 3V3 I External indication of wait B17 SD4_CMD NAND_RE_B 3V3 O GPMC Read Enable F15 NANDF_CS0 NAND_CE...

Page 23: ...EDM1 IMX6PLUS HARDWARE MANUAL VER 1 00 NOV 16 2016 Page 23 of 83 Figure 9 NAND IC Schematics ...

Page 24: ...adio performance make it the best solution for OEM customers who require embedded Wi Fi Bluetooth features The SIP module radio architecture high integration MAC BB chip provide excellent sensitivity with rich system performance In addition to WEP 64 128 WPA and TKIP AES CCX is supported to provide the latest security requirement on your network The SiP module is designed to operate with a single ...

Page 25: ...ed Host device must wake up or remain awake Deserted Host device may sleep when sleep criteria are met The polarity of this signal is software configurable and can be asserted high or low W22 ENET_RXD1 GPIO1_IO26 O WiFi device wake up Signal from the host to the module indicating that the host requires attention Asserted WiFi device must wake up or remain awake Deserted WiFi device may sleep when ...

Page 26: ... O Integrated Interchip Sound I2S channel word clock signal U7 KEY_COL1 AUD5_TXFS O Integrated Interchip Sound I2S channel frame synchronization signal M2 CSI0_DAT12 GPIO5_30 O Low asserting reset for BT core P3 CSI0_DATA_EN GPIO5_IO20 I Host UART wake up Signal from the module to the host indicating that the module requires Attention Asserted Host device must wake up or remain awake Deserted Host...

Page 27: ...EDM1 IMX6PLUS HARDWARE MANUAL VER 1 00 NOV 16 2016 Page 27 of 83 Figure 11 WiFi BT Schematics ...

Page 28: ... internal delay and external delay on Rx path Supports Atheros Green ETHOS power saving modes with internal automatic DSP power saving scheme Supports IEEE 802 3az Energy Efficient Ethernet n Supports SmartEEE which allows MAC SoC devices without 802 3az support to function as the complete 802 3az system Fully integrated digital adaptive equalizers echo cancellers and Near End Crosstalk NEXT cance...

Page 29: ...NET_MDIO MDIO 39 Management data Table 9 EDM Gigabit Ethernet Signal Description EDM Pin Signal V I O Description E3_2 GBE_MDI2 LAN I O Gigabit Ethernet Media Dependent Interface MDI differential pair 2 positive signal E4_2 GBE_MDI0 LAN I O Gigabit Ethernet Media Dependent Interface MDI differential pair 0 positive signal E3_3 GBE_MDI2 LAN I O Gigabit Ethernet Media Dependent Interface MDI differe...

Page 30: ...in the market that has been validated with the EDM1 IMX6PLUS Manufacturer Partnumber Technology Description Pulse Engineering H5007 10 100 1000BaseT Discrete magnetics module Pulse Engineering JK0 0036 10 100 1000BaseT RJ45 jack with integrated magnetics and activity LEDs Bel Fuse S558 5999 P3 10 100 1000BaseT Discrete magnetics module Pulse JW0A1P01R E 10 100 1000BaseT RJ45 jack with integrated m...

Page 31: ...EDM1 IMX6PLUS HARDWARE MANUAL VER 1 00 NOV 16 2016 Page 31 of 83 Figure 12 Gigabit Ethernet Schematics ...

Page 32: ...Serial Interface 2 CSI 2 Version 1 00 29 November 2005 Supports up to 4 Data Lanes Dynamically configurable multi lane merging Long and Short packet decoding Timing accurate signaling of Frame and Line synchronization packets Supports all primary and secondary data formats RGB YUV and RAW color space definitions From 24 bit down to 6 bit per pixel Generic or user defined byte based data types For ...

Page 33: ...unication and Escape Mode Support through Data Lane 0 Programmable display resolutions from 160x120 QQVGA to 1024x768 XVGA Multiple Peripheral Support capability configurable Virtual Channels Video Mode Pixel Formats 16bpp RGB565 18bpp RGB666 packed 18bpp RGB666 loosely 24bpp RGB888 For additional details please refer to the MIPI DSI Host Controller chapter of the i MX6 Reference Manual Table 10 M...

Page 34: ...ace data pair 0 positive signal 20 G2 DSI_D0M DSI_DATA0_M 2V5 O MIPI Camera Serial Interface data pair 0 negative signal 21 GND GND P Ground 22 H4 DSI_CLK0P DSI_CLK0_P 2V5 O MIPI Display Serial Interface clock pair positive signal 23 H3 DSI_CLK0M DSI_CLK0_M 2V5 O MIPI Camera Serial Interface clock pair negative signal 24 GND GND P Ground 25 U5 KEY_COL3 I2C2_SCL 3V3 I O I2C bus clock line 26 T7 KEY...

Page 35: ...sly initialize the test controller The TRST pin has an internal pull up resistor 3 C3 JTAG_TMS I Test Mode Select TMS This is used to sequence the test controller s state machine TMS is sampled on the rising edge of TCK and includes an internal pull up resistor 4 G5 JTAG_TDI I Test Data Input TDI Serial test instruction and data are received through the test data input TDI pin TDI is sampled on th...

Page 36: ...l E3_3 GBE_MDI2 LAN I O Gigabit Ethernet Media Dependent Interface MDI differential pair 2 negative signal E4_3 GBE_MDI0 LAN I O Gigabit Ethernet Media Dependent Interface MDI differential pair 0 negative signal E3_5 GBE_MDI3 LAN I O Gigabit Ethernet Media Dependent Interface MDI differential pair 3 positive signal E4_5 GBE_MDI1 LAN I O Gigabit Ethernet Media Dependent Interface MDI differential p...

Page 37: ... LVDS display standards Synchronization and control capabilities Data input interface inside the i MX6 processor o RGB Data of 18 or 24 bits o Pixel clock o Control signals HSYNC VSYNC DE and 1 additional optional general purpose control I2C Single channel output data output interface o Total of up to 28 bits per data interface are transferred per pixel clock cycle Data Rates o Overall LDB support...

Page 38: ...imary channel differential pair 3 negative signal 17 W1 LVDS0_TX3_P LVDS0_DATA3_P 2V5 O LVDS primary channel differential pair 3 positive signal 21 V4 LVDS0_CLK_N LVDS0_CLK_N 2V5 O LVDS primary channel clock negative signal 23 V3 LVDS0_CLK_P LVDS0_CLK_P 2V5 O LVDS primary channel clock positive signal 27 B19 SD4_DAT1 PWM3_OUT 3V3 O LVDS primary channel panel backlight control 29 D18 SD4_DAT0 GPIO2...

Page 39: ...onal details please refer to the Multimedia chapter of the i MX6 Reference Manual Table 15 HDMI Signal Description EDM PIN i MX6 BALL PAD NAME Signal V I O Description 43 J6 HDMI_CLKP HDMI_TX_CLK_P 3V3 O HDMI differential pair clock positive signal 45 J5 HDMI_CLKM HDMI_TX_CLK_N 3V3 O HDMI differential pair clock negative signal 49 K6 HDMI_D0P HDMI_TX_DATA0_P 3V3 O HDMI differential pair 0 positive...

Page 40: ...SMPTE296 720p Scan Order progressive or interlaced Synchronization Programmable horizontal and vertical synchronization output signals Data enabling output signal The combined data rate for the two DI ports is up to 240 MP sec Supported pixel data formats RGB color depth fully configurable up to 8 bits value color component YUV 4 2 2 8 bits value All mandatory formats in MIPI DBI DPI and DSI For e...

Page 41: ...xel Data bit 12 38 R20 DISP0_DAT13 IPU1_DISP0_DATA13 3V3 O LCD Pixel Data bit 13 40 U25 DISP0_DAT14 IPU1_DISP0_DATA14 3V3 O LCD Pixel Data bit 14 44 T22 DISP0_DAT15 IPU1_DISP0_DATA15 3V3 O LCD Pixel Data bit 15 46 T21 DISP0_DAT16 IPU1_DISP0_DATA16 3V3 O LCD Pixel Data bit 16 50 U24 DISP0_DAT17 IPU1_DISP0_DATA17 3V3 O LCD Pixel Data bit 17 52 V25 DISP0_DAT18 IPU1_DISP0_DATA18 3V3 O LCD Pixel Data b...

Page 42: ... bit data bus of the shared peripheral bus The SPDIF Sony Philips Digital Interface audio module is a stereo transceiver that allows the processor to receive and transmit digital audio over it The SPDIF receiver section includes a frequency measurement block that allows the precise measurement of incoming sampling frequency A recovered clock is provided by the SPDIF receiver section and may be use...

Page 43: ...ry Integrated Interchip Sound I2S channel master clock signal Table 18 Secondary I2 S Audio Signal Description EDM PIN i MX6 BALL PAD NAME Signal V I O Description 186 U6 KEY_ROW1 AUD5_RXD 3V3 I Secondary Integrated Interchip Sound I2S channel receive data line 188 U7 KEY_COL1 AUD5_TXFS 3V3 O Secondary Integrated Interchip Sound I2S channel frame synchronization signal 190 V6 KEY_ROW0 AUD5_TXD 3V3...

Page 44: ...erconnect standard S P DIF can carry two channels of PCM audio or a multi channel compressed surround sound format such as Dolby Digital or DTS The EDM1 IMX6PLUS features an S P DIF interface allowing EDM module to transmit digital audio data The S PDIF interface is implemented by means of the i MX6 integrated S P DIF transceiver For additional details please refer to Sony Philips Digital Interfac...

Page 45: ...scope for easy debug Visibility controllability of hard macro functionality thru programmable registers in the design Over rides on all ASIC side inputs for easy debug Access register space thru simple 16 bit parallel interface Access register space thru JTAG For additional details please refer to the PCI Express PCIe chapter of the i MX6 Reference Manual Table 20 PCI Express Signal Description ED...

Page 46: ... 32 entries For additional details please refer to the Serial Advanced Technology Attachment Controller SATA chapter of the i MX6 Reference Manual Table 21 Serial ATA Signal Description EDM PIN i MX6 BALL PAD NAME Signal V I O Description 123 B14 SATA_RXP SATA_PHY_RX_P 2V5 I Serial ATA channel 1 Receive differential pair positive signal 125 A14 SATA_RXM SATA_PHY_RX_N 2V5 I Serial ATA channel 1 Rec...

Page 47: ...TMI compliant interface High Speed Full Speed and Low Speed operation in Host mode with UTMI transceiver High Speed and Full Speed operation in Peripheral mode with UTMI transceiver Hardware support for OTG signaling session request protocol and host negotiation protocol Up to 8 bidirectional endpoints Support charger detection USB 2 0 Host Controller High Speed Full Speed Low Speed Host Only core...

Page 48: ...H1_VBUS 5V I O Universal Serial Bus power Table 23 USB OTG Signal Description EDM PIN i MX6 BALL PAD NAME Signal V I O Description 141 T2 GPIO_9 GPIO1_IO09 3V3 I Over current detect input pin to monitor USB power over current 155 T4 GPIO_1 USB_OTG_ID 3V3 I Universal Serial Bus On The Go detection signal 157 A6 USB_OTG_DP USB_OTG_DP 3V3 I O Universal Serial Bus differential pair positive signal 159...

Page 49: ...The MMC SD SDIO host controller can support a single MMC SD SDIO card or device For additional details please refer to the Ultra Secured Digital Host Controller uSDHC chapter of the i MX6 Reference Manual Table 24 SDIO MMC Interface Signal Description EDM PIN i MX6 BALL PAD NAME Signal V I O Description 203 T1 GPIO_2 GPIO1_IO02 3V3 I O MMC SDIO Card Detect 205 B21 SD1_CMD SD1_CMD 3V3 I O MMC SDIO ...

Page 50: ... The DMA uses a linked descriptor function with branching capability to automatically handle all of the operations needed to read write multiple pages Data Register Read Write The GPMI can be programmed to read or write multiple cycles to the NAND address command or data registers Wait for NAND Ready The GPMI s Wait for Ready mode can monitor the ready busy signal of a single NAND flash and signal...

Page 51: ...ower Byte Enable Also used for Command Latch Enable 108 A16 NANDF_ALE NAND_ALE 3V3 O GPMC Address Valid or Address Latch Enable 110 E16 SD4_CLK NAND_WE_B 3V3 I GPMC Write Enable 112 B17 SD4_CMD NAND_RE_B 3V3 O GPMC Read Enable 168 C18 NANDF_D7 NAND_DATA07 3V3 I O GPMC data bit 7 170 E17 NANDF_D6 NAND_DATA06 3V3 I O GPMC data bit 6 172 B18 NANDF_D5 NAND_DATA05 3V3 I O GPMC data bit 5 174 A19 NANDF_...

Page 52: ... on the EDM carrier board For additional details please refer to the Flexible Controller Area Network FLEXCAN chapter of the i MX6 Reference Manual Table 26 Primary CAN Bus Signal Description EDM PIN i MX6 BALL PAD NAME Signal V I O Description 200 W6 KEY_COL2 FLEXCAN1_TX 3V3 I O Primary CAN controller Area Network transmit signal 202 W4 KEY_ROW2 FLEXCAN1_RX 3V3 I O Primary CAN controller Area Net...

Page 53: ...RS 232 RS 485 mode RS 485 driver direction control via CTS signal Auto baud rate detection up to 115 2 Kbit s Two independent 32 entry FIFOs for transmit and receive For additional details please refer to the Universal Asynchronous Receiver Transmitter UART chapter of the i MX6 Reference Manual Table 28 Primary UART Signal Description EDM PIN i MX6 BALL PAD NAME Signal V I O Description 241 G21 EI...

Page 54: ...al Asynchronous Receive Transmit secondary channel transmit data signal 238 E18 SD4_DAT4 UART2_RX_DATA 3V3 I Universal Asynchronous Receive Transmit secondary channel receive data signal 240 C19 SD4_DAT5 UART2_RTS_B 3V3 O Universal Asynchronous Receive Transmit secondary channel request to send signal NOTE UART3 is not listed in this section This interface is connected from the i MX6 processor tow...

Page 55: ...le Direct Memory Access DMA support For additional details please refer to the Enhanced Configurable SPI ECSPI chapter of the i MX6 Reference Manual Table 30 Primary SPI Channel Signal Description EDM PIN i MX6 BALL PAD NAME Signal V I O Description 219 J23 EIM_CS1 ECSPI2_MOSI 3V3 O Serial Peripheral Interface primary channel master output slave input signal 221 J24 EIM_OE ECSPI2_MISO 3V3 I Serial...

Page 56: ...ave input signal 224 F21 EIM_D17 ECSPI1_MISO 3V3 I Serial Peripheral Interface secondary channel master input slave output signal 226 C25 EIM_D16 ECSPI1_SCLK 3V3 O Serial Peripheral Interface secondary channel clock signal 228 E22 EIM_EB2 ECSPI1_SS0 3V3 O Serial Peripheral Interface secondary channel Chip Select 0 signal 230 U21 ENET_CRS_DV GPIO1_IO25 3V3 O Serial Peripheral Interface secondary ch...

Page 57: ...73 H20 EIM_D21 I2C1_SCL 5V I O Display ID DDC data line used for HDMI detection If not used this can be assigned to General Purpose I2C bus clock line 75 G23 EIM_D28 I2C1_SDA 5V I O Display ID DDC data line used for HDMI detection If not used this can be assigned to General Purpose I2C bus data line NOTE The 5 0V I2C signals are normally connected towards the external HDMI display interface and sh...

Page 58: ...BALL PAD NAME Signal V I O Description 231 U5 KEY_COL3 I2C2_SCL 3V3 I O I2C bus clock line 233 T7 KEY_ROW3 I2C2_SDA 3V3 I O I2C bus data line Table 34 Secondary General Purpose I2 C Bus Signal Description EDM PIN i MX6 BALL PAD NAME Signal V I O Description 235 R4 GPIO_5 I2C3_SCL 3V3 I O I2C bus clock line 237 R2 GPIO_16 I2C3_SDA 3V3 I O I2C bus data line NOTE All I2C bus data and clock lines for ...

Page 59: ...Signal V I O Description 255 L6 CSI0_DAT19 GPIO6_IO05 3V3 I O General Purpose Input Output 256 L4 CSI0_DAT16 GPIO6_IO02 3V3 I O General Purpose Input Output 257 M6 CSI0_DAT18 GPIO6_IO04 3V3 I O General Purpose Input Output 258 E25 EIM_D27 GPIO3_IO27 3V3 I O General Purpose Input Output 259 E24 EIM_D26 GPIO3_IO26 3V3 I O General Purpose Input Output 260 N22 EIM_BCLK GPIO6_IO31 3V3 I O General Purpo...

Page 60: ... manufacturing and validation purposes 273 L23 EIM_DA5 SRC_BOOT_CFG05 I Pins for manufacturing and validation purposes 275 K25 EIM_DA6 SRC_BOOT_CFG06 I Pins for manufacturing and validation purposes 277 L25 EIM_DA7 SRC_BOOT_CFG07 I Pins for manufacturing and validation purposes 278 M20 EIM_DA11 SRC_BOOT_CFG11 I Pins for manufacturing and validation purposes 280 M24 EIM_DA12 SRC_BOOT_CFG12 I Pins f...

Page 61: ...n EDM1 FAIRY evaluation carrier board You can simply configure the EDM MNF BOOT PCB that comes with the EDM1 FAIRY START evaluation kit as follow Table 38 EDM MNF BOOT Configuration for EDM1 FAIRY SATA SD Cardslot eMMC on Carrier board Figure 13 EDM1 FAIRY with EDM MNF BOOT PIN 1 is marked with a White dot ...

Page 62: ...il Nominal Input Input Range Maximum Input Ripple VCC 18 pin 5V 4 75V 5 25V 50 mV 5VSB 2 pin 5VSB 4 75V 5 25V 50 mV 3 17 1 Power Management Signals The EDM1 IMX6PLUS has the following set of signals to control the system power states such as the power on and reset conditions This enables the system designer to implement a fully ACPI compliant system supporting system states The minimum hardware re...

Page 63: ...gn an RTC circuit on the EDM carrier board For example the Maxim Integrated DS1337 connected over the general purpose I2C can be used Start Sequence VCC_RTC must come up at the same time or before VCC comes up Stop Sequence VCC must go down at the same time or before VCC_RTC goes down Table 40 Input Power Sequencing for AT based configurations Item Description Value T1 VCC_RTC rise to VCC rise 0 m...

Page 64: ...s up 5VSB must come up at the same time or before VCC comes up A 5V return signal is generated on EDM PIN 251 PWGIN must be active at the same time or after VCC comes up Stop Sequence PWGIN must be inactive at the same time or before VCC goes down VCC must go down at the same time or before 5VSB goes down 5VSB must go down at the same time or before VCC_RTC goes down Table 41 Input Power Sequencin...

Page 65: ...6PLUS provides support to be powered without a carrier board by mounting a power connector that provides 5V to the System on Module directly A Molex 43650 0200 connector should be mounted at the following location Figure 16 EDM1 IMX6PLUS Optional Power Connector Location Figure 17 EDM1 IMX6PLUS with mounted Molex 43650 0200 Connector ...

Page 66: ...y 5VDC 5 E1_4 VCC 5V P Power Supply 5VDC 5 E2_4 VCC 5V P Power Supply 5VDC 5 E1_5 VCC 5V P Power Supply 5VDC 5 E2_5 VCC 5V P Power Supply 5VDC 5 E1_6 VCC 5V P Power Supply 5VDC 5 E2_6 VCC 5V P Power Supply 5VDC 5 E1_7 VCC 5V P Power Supply 5VDC 5 E2_7 VCC 5V P Power Supply 5VDC 5 E1_8 VCC 5V P Power Supply 5VDC 5 E2_8 VCC 5V P Power Supply 5VDC 5 E1_9 VCC 5V P Power Supply 5VDC 5 E2_9 VCC 5V P Pow...

Page 67: ...n 19 GBE_MDI3 LAN I O Gigabit Ethernet Media Dependent Interface MDI differential pair 3 negative signal E4_6 AR8035 pin 13 GBE_MDI1 LAN I O Gigabit Ethernet Media Dependent Interface MDI differential pair 1 negative signal E3_7 AR8035 pin 21 LED1_ACT 3V3 O Gigabit Ethernet LED Activity indicator E4_7 GND GND P Ground E3_8 GND GND P Ground E4_8 AR8035 pin 24 LED1_nLink100 3V3 O Gigabit Ethernet 10...

Page 68: ... GND P Ground 19 GND GND P Ground 20 R23 DISP0_DAT6 IPU1_DISP0_DATA06 3V3 O LCD Pixel Data bit 6 21 V4 LVDS0_CLK_N LVDS0_CLK_N 2V5 O LVDS primary channel clock negative signal 22 R24 DISP0_DAT7 IPU1_DISP0_DATA07 3V3 O LCD Pixel Data bit 7 23 V3 LVDS0_CLK_P LVDS0_CLK_P 2V5 O LVDS primary channel clock positive signal 24 GND GND P Ground 25 GND GND P Ground 26 R22 DISP0_DAT8 IPU1_DISP0_DATA08 3V3 O ...

Page 69: ...ential pair 0 negative signal 52 V25 DISP0_DAT18 IPU1_DISP0_DATA18 3V3 O LCD Pixel Data bit 18 53 GND GND P Ground 54 GND GND P Ground 55 J4 HDMI_D1P HDMI_TX_DATA1_P 3V3 O HDMI differential pair 1 positive signal 56 U23 DISP0_DAT19 IPU1_DISP0_DATA19 3V3 O LCD Pixel Data bit 19 57 J3 HDMI_D1M HDMI_TX_DATA1_N 3V3 O HDMI differential pair 1 negative signal 58 U22 DISP0_DAT20 IPU1_DISP0_DATA20 3V3 O L...

Page 70: ...l 83 GND GND P Ground 84 RSVD Reserved 85 D7 CLK1_P XTALOSC_CLK1_P 2V5 O PCI Express channel A clock differential pair positive signal 86 F15 NANDF_CS0 NAND_CE0_B 3V3 O GPMC Chip Select bit A 87 C7 CLK1_N XTALOSC_CLK1_N 2V5 O PCI Express channel A clock differential pair negative signal 88 GND GND P Ground 89 GND GND P Ground 90 C16 NANDF_CS1 NAND_CE1_B 3V3 O GPMC Chip Select bit B 91 B3 PCIE_TXP ...

Page 71: ...15 NC Not Connected 116 NC Not Connected 117 NC Not Connected 118 NC Not Connected 119 H21 EIM_D31 GPIO3_IO31 3V3 O PCI Express Reset signal for external devices 120 NC Not Connected 121 GND GND P Ground 122 NC Not Connected 123 B14 SATA_RXP SATA_PHY_RX_P 2V5 I Serial ATA channel 1 Receive differential pair positive signal 124 GND GND P Ground 125 A14 SATA_RXM SATA_PHY_RX_N 2V5 I Serial ATA channe...

Page 72: ...niversal Serial Bus differential pair positive signal 158 NC Not Connected 159 B6 USB_OTG_DN USB_OTG_DN 3V3 I O Universal Serial Bus differential pair negative signal 160 NC Not Connected 161 E9 USB_OTG_ VBUS USB_OTG_ VBUS 5V I O Universal Serial Bus power 162 NC Not Connected 163 E23 EIM_D22 USB_OTG_PWR USB O Universal Serial Bus power enable 164 NC Not Connected 165 J20 EIM_D30 USB_H1_OC 3V3 I O...

Page 73: ... 190 V6 KEY_ROW0 AUD5_TXD 3V3 O Secondary Integrated Interchip Sound I2S channel transmit data line 191 P2 CSI0_DAT5 AUD3_TXD 3V3 O Primary Integrated Interchip Sound I2S channel transmit data line 192 W5 KEY_COL0 AUD5_TXC 3V3 O Secondary Integrated Interchip Sound I2S channel word clock signal 193 N1 CSI0_DAT4 AUD3_TXC 3V3 O Primary Integrated Interchip Sound I2S channel word clock signal 194 T5 ...

Page 74: ...pheral Interface primary channel master input slave output signal 222 D24 EIM_D18 ECSPI1_MOSI 3V3 O Serial Peripheral Interface secondary channel master output slave input signal 223 H24 EIM_CS0 ECSPI2_SCLK 3V3 O Serial Peripheral Interface primary channel clock signal 224 F21 EIM_D17 ECSPI1_MISO 3V3 I Serial Peripheral Interface secondary channel master input slave output signal 225 K20 EIM_RW EC...

Page 75: ...5 M3 CSI0_DAT11 UART1_RX_DATA 3V3 I Universal Asynchronous Receive Transmit secondary channel receive data signal 246 NC Not Connected 247 G20 EIM_D20 UART1_RTS_B 3V3 O Universal Asynchronous Receive Transmit secondary channel request to send signal 248 NC Not Connected 249 GND GND P Ground 250 GND GND P Ground 251 5VSB with 10KΩ S3 3V3 O S3 signal shuts off power to all runtime system components ...

Page 76: ...EIM_DA4 SRC_BOOT_CFG04 I Pins for manufacturing and validation purposes 272 NC Not Connected 273 L23 EIM_DA5 SRC_BOOT_CFG05 I Pins for manufacturing and validation purposes 274 NC Not Connected 275 K25 EIM_DA6 SRC_BOOT_CFG06 I Pins for manufacturing and validation purposes 276 NC Not Connected 277 L25 EIM_DA7 SRC_BOOT_CFG07 I Pins for manufacturing and validation purposes 278 M20 EIM_DA11 SRC_BOOT...

Page 77: ..._DATA14 AUD5_RXC GPIO5_IO08 44 T22 DISP0_DAT1 5 IPU1_DISP0 _DATA15 IPU2_DISP0 _DATA15 ECSPI1_SS1 ECSPI2_SS1 GPIO5_IO09 46 T21 DISP0_DAT1 6 IPU1_DISP0 _DATA16 IPU2_DISP0 _DATA16 ECSPI2_MO SI AUD5_TXC SDMA_EXT_ EVENT0 GPIO5_IO10 50 U24 DISP0_DAT1 7 IPU1_DISP0 _DATA17 IPU2_DISP0 _DATA17 ECSPI2_MIS O AUD5_TXD SDMA_EXT_ EVENT1 GPIO5_IO11 52 V25 DISP0_DAT1 8 IPU1_DISP0 _DATA18 IPU2_DISP0 _DATA18 ECSPI2_...

Page 78: ...T_RX_D ATA3 AUD5_TXC KEY_COL0 UART4_TX_ DATA GPIO4_IO06 DCIC1_OUT 193 N1 CSI0_DAT4 IPU1_CSI0_ DATA04 EIM_DATA0 2 ECSPI1_SC LK KEY_COL5 AUD3_TXC GPIO5_IO22 ARM_TRAC E01 194 T5 GPIO_0 CCM_CLKO 1 KEY_COL5 ASRC_EXT_ CLK EPIT1_OUT GPIO1_IO00 USB_H1_P WR SNVS_VIO_ 5 195 T5 GPIO_0 CCM_CLKO 1 KEY_COL5 ASRC_EXT_ CLK EPIT1_OUT GPIO1_IO00 USB_H1_P WR SNVS_VIO_ 5 196 W2 ENET_RXD0 XTALOSC_O SC32K_32K _OUT ENET...

Page 79: ..._DI0_PI N08 IPU2_CSI1_ DATA16 UART1_CTS _B GPIO3_IO19 EPIT1_OUT 243 M1 CSI0_DAT10 IPU1_CSI0_ DATA10 AUD3_RXC ECSPI2_MIS O UART1_TX_ DATA GPIO5_IO28 ARM_TRAC E07 245 M3 CSI0_DAT11 IPU1_CSI0_ DATA11 AUD3_RXFS ECSPI2_SS0 UART1_RX_ DATA GPIO5_IO29 ARM_TRAC E08 247 G20 EIM_D20 EIM_DATA2 0 ECSPI4_SS0 IPU1_DI0_PI N16 IPU2_CSI1_ DATA15 UART1_RTS _B GPIO3_IO20 EPIT2_OUT 255 L6 CSI0_DAT19 IPU1_CSI0_ DATA19 ...

Page 80: ... mass produce solutions with our EDM System on Modules 6 1 Product Ordering Part Numbers The EDM1 IMX6PLUS is available in a number of standard configurations Custom tailored versions with other memory configuration de population of interfaces or extended and industrial temperature options are available upon request 6 1 1 Standard Part Numbers Standard part numbers can be easily found on the EDM1 ...

Page 81: ...ssor S i MX6 Solo U i MX6 Duallite D i MX6 Dual Q i MX6 Quad QP i MX6 QuadPlus Memory R05 512 MB DDR3 R10 1GB DDR3 R20 2GB DDR3 Storage E04 eMMC 4GB Default Exx Other capacities of eMMC are possible 8GB 16GB 32GB 64GB N05 512 MB NAND Flash IC Nxx NAND Flash IC other capacity 1GB 2GB Wireless Networking No BB 802 11bgn Bluetooth 4 1 BCM43438 BW 802 11ac Bluetooth 4 1 BCM4339 Temperature Range Comme...

Page 82: ...ents or other intellectual property of the third party or a license from TechNexion under the patents or other intellectual property of TechNexion TechNexion products are not authorized for use in safety critical applications such as life support where a failure of the TechNexion product would reasonably be expected to cause severe personal injury or death unless officers of the parties have execu...

Page 83: ...this publication To the extent permitted by law no liability including liability to any person by reason of negligence will be accepted by TechNexion Ltd its subsidiaries or employees for any direct or indirect loss or damage caused by omissions from or inaccuracies in this document TechNexion Ltd reserves the right to change details in this publication without notice Product and company names her...

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