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8. Timing Chart
●
Pixel clock timing (common in various operation modes)
[Phase relationship between clock output and data]
１ ＣＬ Ｋ ＝１ ７ ． ５ｎ Ｓ
９ ｎ Ｓmax .
Cl o ck si gn a l
Di g it a l vi d e d at a
（Ｄ ９ ～ Ｄ０ ）
Ｌ Ｖ Ｄ s i gn a l
Ｆ Ｖ Ｄ s i gn a l
５ ｎＳ max .
Ap pro x. １ ．３ μ Ｓ
Ｌ Ｖ Ｄ s i gn a l
※Ch ange th e s ett ings on th e c aptu re boa rd side or ca mera si de
a s th e d ata ge t un sta ble if the y a re retr iev ed
at abo ve poi nt of t ime .
(Note) The above timing represents the signal timing before being encoded to serial data by the channel link device on the
side of the sending end (the part circled in the above right figure). If signal conversion from serial to parallel is made by
a channel link device in accordance with the Camera Link standard on the side of the receiving end, the phase
relationship between the clock and the data after decoding will be different from that of the above timing due to the
structural nature of a channel link device. (In the case of the output from a channel link device, the data are aligned
with the trailing edge of the clock signal.) As a general rule, this variation in timing is correctly adjusted at the capture
timing of a capture board, the equal definition file to that of the conventional parallel output type can be used for
capturing.
(!) 10 bit x 2 tap output is employed for FC1500FCL. Therefore, there is no compatibility with the conventional parallel type
camera FC1500F . and so dedicated setting files are required.
(!) Each timing signal output for “BUSY” which is included as standard for FC1500F is omitted for FC1500FCL.
(Note) When a channel link device is mounted directly to the capture interface on the user side, instead of using a
commercially available capture board that supports Camera Link, it is necessary to pay close attention to the
descriptions of the data sheet of the channel link device including the phase relationship between data and clock prior to
the use.
●
Horizontal timing (common in various operation modes)
ＨＤ
ＣＣＤ output signal
Ｏ Ｂ
１
Ho rizo nta l t ran sfer
su spen sio n p eri od
Du mmy
bi t
Ｏ Ｂ
４ ０
３１ ５
２ ０
２
１
１ ５ ７
Eff ect ive pix els
１３ ９ ２
１
３７ ７
１hor izo ntal pe rio d （１ Ｈ ）
２
４
３
５
１
３
９
２
（ Int ern al hor izo nt al
s ync si gna l）
１ ７ ９ ０
１
３
９
２
Digital output
（ＣＨ１，２）
８ Ｃ
７ ６ Ｃ
Ef fec tiv e im age du rat ion （ １ ３９ ０pi xel s ）
６ ９５ Ｃ
９ ４ Ｃ
３ ０ Ｃ
Di git al
ＬＤＶ
ＣＬＫ
3
4
1 387
1 388
5
6
7
8
139 1
139 2
1389
1390
１ Ｃ
（ ２ ）
HSYNC
* Unless otherwise specified, the time unit of the numbers in the horizontal timing chart is operation CLK(=1/57.273MHz
≒
17.5nS).
And CLK output 1C= 1/28.636MHz
≒
34.9nS.
* The numbers shown here are design values, and the actual equipment should be checked for the details.
Ａ／Ｄ
１０ｂｉｔ
Camera L ink
conne ctor
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SYNC
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