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DLD8080 R4.30 & R4.31 Manual
6.2 Delayline Detector - Connection Ports
The base flange of the delayline detector carries three CF40 flanges. One holds three single SHV
feedthroughs for the high voltage supply of the detector and the other one holds 4 SMB feedthroughs for
signal transfer (see
). The flange for the signal transfer also holds an orientation pin for correct
orientation of the ACU. The allocation of the four signal channels X1, X2, Y1 and Y2 on the “SMB flange” can
be taken from
.
The naming of the SHV connections are engraved directly on the CF40 flange. The internal high voltage
connection for the delayline detector is given schematically in
. The third CF40 flange is a spare
port for future extensions on the detector (e.g. additional pulse readout of the MCP stack directly).
Do not disconnect single high voltage cables from the delayline detector as long as high
voltage is applied. This will lead to sparks which can damage the very sensitive detector,
the MCPs and/or the analogue readout electronics seriously.
Figure 10: Connection ports for the DLD8080 R4.30 & R4.31.
Figure 11: Internal connection of high voltage potentials (schematic).
The resistance between MCP front and MCP back (resistance of MCP stack) should be
in the range of 8 – 30 MΩ (the exact value is given in the specification sheet of your
detector).
Note
DLD8080 R4.30 & R4.31 Manual | Surface Concept GmbH
