Chapter 2: Installation
2-23
JMLP_STBY2
X10DRFR
BAR CODE
JI2C1
JWD1
JPB1
JPL1
JITP1
JPP0
JPP1
JTPM1
JSD1
JSD2
FAN3
FAN1
FAN2
JIPMB1
JBT1
JF1
T-SGPIO1 T-SGPIO2
JNMI1
LE1
LE2
LEDM1
LE3
JPWR10
JPWR9
JBAT1
CPU1
CPU2
I-SA
TA0
I-SA
TA1
I-SATA3
I-SA
TA4
S-SA
TA3
S-SA
TA2
GND
12V_IN
IPMI_LAN
LAN2 LAN1
COM1
USB1(3.0)
USB0(3.0)
CPU1 SXB1 PCI-E 3.0 X16
CPU1 MLP
PCI-E 3.0 X8
CPU1 SXB2 PCI-E 3.0 X8
P2-DIMME1
P2-DIMME2
P2-DIMMF1
P2-DIMMF2
P2-DIMMH2
P2-DIMMH1
P2-DIMMG1
P2-DIMMG1
P1-DIMMA1 P1-DIMMA2 P1-DIMMB1 P1-DIMMB2
P1-DIMMD2 P1-DIMMD1 P1-DIMMC2 P1-DIMMC1
POWER BUTTON
JPG1
I-SA
TA5
BIOS
VGA
S-SA
TA1
S-SA
TA0
Rev. 1.10
1
1
CLOSE 1st
OPEN 1st
PCH
LAN
CTRL
BMC
I-SA
TA2
1
FAN4
JPME2
JI2C2
JHP_I2C1
JVRM2
Battery
JMLP_STBY1
HDDPOWER1
HDDPOWER3
JNVME2JNVME1
LE4
HDDPOWER2
JVRM1
JNVI2C1
A. T-SGPIO 1
B. T-SGPIO 2
C. JNVME1
D. JNVME2
A
T-SGPIO 1/2 Headers
Two SGPIO (Serial-Link General Purpose Input/
Output) headers (T-SGPIO 1/2) are located
on the motherboard. These headers support
Serial_Link interface for onboard SATA connec-
tions (T-SGPIO1: for I-SATA0-5, T-SGPIO2: for
S-SATA0-3). See the table on the right for pin
definitions.
T-SGPIO
Pin Definitions
Pin# Definition
Pin Definition
1
NC
2
NC
3
Ground
4
Data
5
Load
6
Ground
7
Clock
8
NC
B
NVM Express Connections (For X10DRFR-N/NT Only)
Two NVM Express ports are located on the motherboard. JNVME ports 1/2 pro-
vide high-speed, low-latency PCI-Exp. 3.0 x4 connections directly from the CPU
to NVMe Solid State (SSD) drives. This greatly increases SSD data-throughput
performance and significantly reduces PCI-E latency by simplifying driver/
software requirements resulted from direct PCI-E interface from the CPU to the
NVMe SSD drives.
C
D
