2-22
X10DRFR/X10DRFR-N/X10DRFR-NT Motherboard User’s Manual
JMLP_STBY2
X10DRFR
BAR CODE
JI2C1
JWD1
JPB1
JPL1
JITP1
JPP0
JPP1
JTPM1
JSD1
JSD2
FAN3
FAN1
FAN2
JIPMB1
JBT1
JF1
T-SGPIO1 T-SGPIO2
JNMI1
LE1
LE2
LEDM1
LE3
JPWR10
JPWR9
JBAT1
CPU1
CPU2
I-SA
TA0
I-SA
TA1
I-SATA3
I-SA
TA4
S-SA
TA3
S-SA
TA2
GND
12V_IN
IPMI_LAN
LAN2 LAN1
COM1
USB1(3.0)
USB0(3.0)
CPU1 SXB1 PCI-E 3.0 X16
CPU1 MLP
PCI-E 3.0 X8
CPU1 SXB2 PCI-E 3.0 X8
P2-DIMME1
P2-DIMME2
P2-DIMMF1
P2-DIMMF2
P2-DIMMH2
P2-DIMMH1
P2-DIMMG1
P2-DIMMG1
P1-DIMMA1 P1-DIMMA2 P1-DIMMB1 P1-DIMMB2
P1-DIMMD2 P1-DIMMD1 P1-DIMMC2 P1-DIMMC1
POWER BUTTON
JPG1
I-SA
TA5
BIOS
VGA
S-SA
TA1
S-SA
TA0
Rev. 1.10
1
1
CLOSE 1st
OPEN 1st
PCH
LAN
CTRL
BMC
I-SA
TA2
1
FAN4
JPME2
JI2C2
JHP_I2C1
JVRM2
Battery
JMLP_STBY1
HDDPOWER1
HDDPOWER3
JNVME2JNVME1
LE4
HDDPOWER2
JVRM1
JNVI2C1
A
TPM Header/Port 80
A Trusted Platform Module/Port 80 head-
er is located at JTPM1 to provide TPM
support and Port 80 connection. Use this
header to enhance system performance
and data security. See the table on the
right for pin definitions.
TPM/Port 80 Header
Pin Definitions
Pin # Definition
Pin # Definition
1
LCLK
2
GND
3
LFRAME#
4
<(KEY)>
5
LRESET#
6
+5V (X)
7
LAD 3
8
LAD 2
9
+3.3V
10
LAD1
11
LAD0
12
GND
13
SMB_CLK4
14
SMB_DAT4
15
+3V_DUAL
16
SERIRQ
17
GND
18
CLKRUN# (X)
19
LPCPD#
20
LDRQ# (X)
A. TPM/Port80
B. JNMI1
Non-Mask Interrupt Header
A Non-Mask Interrupt header is located at
JNMI1 to provide NMI1 connection. Use
this header to enhance system. See the
layout for the location.
B
NMI Button
Pin Definitions
Pin# Definition
1
Control
2
Ground
