Supero SuperServer 6024H-32, User Manual

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ERVER 6024H-32R/6024H-32 User's Manual
Advanced Chipset Control
Access the submenu to make changes to the following settings.
* Warning
: Take Caution when changing the Advanced settings. Incorrect
values entered may cause system malfunction. Also, a very high DRAM
frequency or incorrect DRAM timing may cause system instability. When this
occurs, revert to the default setting.
Force Compliance Mode
This feature allows you to enable the PCI-Express Compliance Mode. The options
are: Disabled or Enabled.
Memory RAS Feature Control
Select this option in order to enable the special feature of DIMM sapring or memory
mirroring. The options are Mirroring, Sparing and Standard .
Clock Spectrum Feature
If "Enabled", BIOS will monitor the level of Electromagnetic Interference caused by
the components and will attempt to decrease the interference whenever needed.
The options are Enabled and Disabled .
Memory Remap Function Control
Select Enabled to re-allocate memory resource for PCI slots. The options are
Enabled and Disabled.
Delayed Transaction Discard Timer
Select Enabled to set Discard Timer at 64us for PCI 32 bus use. Select Disabled
to set Discard Timer at 32us for PCI 32 bus use. The options are Enabled and
Disabled .
DRAM Data Integrity Mode
If enabled, this feature allows the data stored in the DRMA memory to be integrated
for faster data processing. The options are 72-bit ECC, 144-bit ECC, Auto and
Disabled.
ECC Error Type
This setting lets you select which type of interrupt to be activated as a result of an
ECC error. The options are None, NMI (Non-Maskable Interrupt), SMI (System
Management Interrupt) and SCI (System Control Interrupt.)
SERR Signal Condition
This setting specifi es the ECC Error conditions that an SERR# is to be asserted.
The options are None, Single Bit , Multiple Bit and Both.