Supero Supero X9DRFF, User Manual

Page: 48 / 107

2-24
X9DRFF/X9DRFF-7 Motherboard User’s Manual
VGA1
SP1
LED1 LED2 LED5
P1-DIMMC
1
P1-DIMMD
1
P2-DIMME
1
P2-DIMMF1
P2-DIMMG
1
P2-DIMMH
1
SW1
JTPM
1
JPS1
JPL2
JPL1
JPG1
JBR1
JWP1
JPB1
JSTBY1
DP1
JIPMB1
L-SAS0
L-SAS1
L-SAS2
L-SAS3
I-SATA1
I-SATA5
I-SATA4
I-SATA3
I-SATA2
JSD1 JP3
T-SGPIO1
T-SGPIO2
6-SGPIO1
JI2C
2
JI2C
1
JFLED1
JFLED2
JP
5
X9DRFF
Rev. 1.10A
USB2
USB1
L-SAS4-7
IPMI_LAN
UI
D
LAN2 LAN1
COM1
FA
N2
FA
N1
BATTERY
CPU2 SLOT2 PCI-E 3.0 X1
6
CPU2
CPU1
CPU1 Slot1 PCI-E 3.0 X1
6
USB0
I-SATA0
JWD1
JPVR_I2C
1
JPVR_I2C
2
P1-DIMMA
1
P1-DIMMB
1
LEDS2
LED3
BIOS
BUZZER
JBT1
BMC
CTRL
Intel
PCH
SAS
CTRL
LAN
CTRL
LAN
CTRL
JP4
CLOSE 1st
OPEN 1st
CLOSE 1st
OPEN 1st
D
A
B
A. T-SGPIO1
B. T-SGPIO2
C . 6 - S G P I O 1 ( f o r
X9DRFF-7 only)
D. PWR Connector to
Failed System LED
T-SGPIO1/2 & 6-SGPIO1 Headers
Two SGPIO (Serial-Link General Purpose Input/
Output) headers are located on the motherboard.
In addition, a 6-SGPIO1 is located on X9DRFF-7
motherboard. These headers support onboard Se-
rial_Link interface connections.
Note: T-SGPIO 1/2 support onboard SATA
connections. 6-SGPIO1 supports SAS
interface for X9DRFF-7.
Note: NC= No Connection
T-SGPIO/6-SGPIO
Pin Definitions
Pin# Definition Pin Definition
2 NC 1 NC
4 Ground 3 Data
6 Load 5 Ground
8 Clock 7 NC
C
Power Connector Header for Failed System
LED Header
A power connector for the Failed System LED is
located at JFLED1. Connect an appropriate cable
here to provide power from an external battery to
the Failed System LED used to identify a failed
system. See the table on the right for pin definitions.
PWR Connector for
Failed System LED
Pin Definitions
Pin# Definition
1 +3V Input
2 Ground