Supero Supero PDSMA, User Manual

Page: 59 / 101

Chapter 4: BIOS
4-11
Enable Master
This setting allows you to enable the selected device as the PCI bus master.
The options are Enabled and Disabled.
Latency Timer
This setting allows you to set the clock rate for Bus Master. A high-priority, high-
throughout device may benefi t from a greater clock rate. The options are Default ,
0020h, 0040h, 0060h, 0080h, 00A0h, 00C0h, and 00E0h. For Unix, Novell and
other Operating Systems, please select the option: other. If a drive fails after the
installation of a new software , you might want to change this setting and try
again. A different OS requires a different Bus Master clock rate .
Large Disk Access Mode
This setting determines how large hard drives are to be accessed. The options
are DOS or Other (for Unix, Novelle NetWare and other operating systems).
u
Advanced Chipset Control
Access the submenu to make changes to the following settings.
*
Warning : Take Caution when changing the Advanced settings. Incorrect
values entered may cause system malfunction. Also, a very high DRAM
frequency or incorrect DRAM timing may cause system instability. When this
occurs, revert to the default setting.
Clock Spectrum Feature
If Enabled, the BIOS will monitor the level of Electromagnetic Interference caused
by the components and will attempt to decrease the interference whenever needed.
The options are Enabled and Disabled .
ECC Conditions
This setting specifi es the ECC Error conditions that will be treated as "ECC Error
Events" by the system. The options are None, Single Bit, Multiple Bit, and Both.
(*Note: This item is available when it is supported by the memory.)
ECC Error Handler
This setting allows you to select the type of interrupt to be activated as a result of
an ECC error. The options are None, NMI (Non-Maskable Interrupt), SMI (System
Management Interrupt) and SCI (System Control Interrupt.)
(*Note: This item is
available when it is supported by the memory.)
Route Port 80h Cycles to
This feature allows the user to decide which bus to send the debug information to.
The options are PCI and LPC.