S
UPER P3TDDR User's Manual
4-10
Host & AGP Bridge Control
This section documents the AwardBIOS management of the bus links
between host and bridge devices.
Memory Parity / ECC Check
"Enabled" adds a parity check to the boot-up memory tests. Select "Enabled"
only if the system DRAM contains parity. Settings are "Enabled" and
"Disabled".
System BIOS Cacheable
If enabled, the system BIOS information stored in the BIOS ROM (Read Only
Memory) chip will be written and temporarily stored in the "cacheable"
section of the memory, so the CPU has faster access to the information.
The settings are "Enabled" and "Disabled".
Video BIOS Shadow
If enabled, the Video BIOS information stored in the BIOS ROM (Read Only
Memory) chip will be written and temporarily stored in the "cacheable"
section of the memory to provide faster access to the information. The
settings are "Enabled" and "Disabled".
Memory Hole
To improve the performance of the sytem, a certain section of the memory
will be reserved for the use of the devices installed in the PCI slots. This
section of memory must be mapped into the memory space below 16MB.
The settings are "15M-16M" and "Disabled".
CPU to PCI Write Buffer
To improve the performance of the system, a certain section of the memory
will be designated as "Write Buffer" to temporarily store the data CPU writes
to PCI to provide faster access. This information can be exe.codes or
operational instructions for the system. The settings are "Enabled" and
"Disabled".
