Supero C9X299-PG, User Manual

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Supermicro C9X299-PG/-PGF/-RPGF Motherboard User’s Manual
RH Activation Probability
This feature controls Row Hammer Activation probability. The options are
1/2^2, 1/2^3, 1/2^4, 1/2^5, 1/2^6, 1/2^7, 1/2^8, 1/2^9, 1/2^10,
1/2^11 , 1/2^12, 1/2^13, 1/2^14, 1/2^15.
Exit on Failure (MRC)
This feature enables Exit on Failure for MRC training steps. The options
are Disabled or
Enabled .
MC Lock
This feature enables the ability to lock MC registers. The options are
Disabled or
Enabled .
Probeless Trace
This feature controls probeless trace configuration. The options are Dis-
abled , GDXC IOT/MOT, and HD Port.
Enable/Disable IED (Intel Enhanced Debug)
This feature controls whether Intel® Enhanced Debug is enabled or not.
Ch Hash Support
When memory is interleaved, this feature enables Channel Hash support.
Ch Hash Mask
Enter a value for the BIT(s) to be included in the XOR function.
Ch Hash Interleaved Bit
Select the BIT to use for Channel Interleaved mode. BIT7 interleaves
at 2 cacheline granularity; BIT8 at 4 granularity; BIT9 at 8 granularity.
The options are BIT6, BIT7,
BIT8 , BIT9, BIT10, BIT11, BIT12, BIT13.
VC1 Read Metering
This feature enables VC1 Read Metering. The options are Disabled or
Enabled .
VC1 RdMeter Time Window
Enter a value for the time window during which the VC1 Read request
counter is tracked. Configurable in tens of microseconds. Default is 800 .
VC1 RdMeter Threshold
Enter a value for the time window counter threshold. Default is 280 .