2-18
X10SLH-LN6TF User’s Manual
A
IPMI CODE
C A
BIOS
LICENSE
BAR CODE
MAC CODE
C
A
A
C
A
C
A
+
JLAN3
JLAN2
JLAN1
JP1000
JPW
1
JPW2
JSTBY1
J4
LE6
DIMM1 DIMM2
DIMM4
DIMM3
FAN4
FA
N3
FAN2 FAN1
FANA
JPME1
JI2C1
JPME2
JI2C2
JPUSB1
JPL1
JPL2
JPL3
JPG
1
JBR
1
JWD1
JLED
1
LE5
LE
4
LE1
LE
3
J3
JL
1
JLED_LAN
4
JLED_LAN
3
JLED_LAN6
JLED_LAN
5
JPI2C1
JTPM1
T-SGPIO1
T-SGPIO2
JSD2
JSD1
SPKR1
B1
JBT1
JF
1
SW
1
COM1
COM2
PCH SLOT4 PCI-E 2.0 X4(IN X8
)
DESIGNED IN USA
X10SLH-LN6TF
REV:1.01
USB0(3.0)
USB1(3.0)
USB12/13
USB8/9
CPU SLOT6 PCI-E 3.0 X8(IN X16)
I-SA
TA
0
I-SA
TA
2
I-SA
TA
1
I-SA
TA
3
I-SA
TA
4
I-SA
TA
5
VGA
LAN5/6
LAN3/4
LAN1/2
USB4/5 (2.0)
USB2/3(3.0)
JLED1:3 pin Power LED
IPMI LAN
JF
1
NIC2
NIC1
ON
PWR
X
RST
OH/
FF
LED
LED
HDD
X
PWR
NMI
C226
X540
X540
X540
BMC
PLX
A. Backpanel USB 4 (2.0)
B. Backpanel USB 5 (2.0)
C. Backpanel USB 3 (3.0)
D. Backpanel USB 2 (3.0)
E. Front USB 8/9 (2.0)
F. Front USB 12/13 (2.0)
G. Type A USB 0 (3.0)
H. Front Accessible USB 1 (3.0)
Universal Serial Bus (USB)
Two Universal Serial Bus 3.0 ports (USB2/3) and two USB 2.0 ports (USB4/5) are
located on the I/O back panel. In addition, two USB 2.0 headers (four USB 2.0 con
-
nections: 8/9, 12/13), a Type A USB 3.0 header (USB0), and a front accessible USB
3.0 header (USB1) are also located on the motherboard to provide front chassis
access using USB cables (not included). See the tables below for pin definitions.
Front Panel USB (2.0) 8/9, 12/13
Pin Definitions
Pin # Definition
Pin # Definition
1
+5V
2
+5V
3
USB_PN2
4
USB_PN3
5
USB_PP2
6
USB_PP3
7
Ground
8
Ground
9
Key
10
Ground
A
Front Panel USB (3.0) 1
Pin Definitions
Signal Name Description
1
VBUS
Power
2
D-
USB 2.0 Differential Pair
3
D+
4
Ground
Ground of PWR Return
5
StdA_SSRX-
SuperSpeed Receiver
6
St
Differential Pair
7
GND_DRAIN
Ground for Signal Return
8
StdA_SSTX-
SuperSpeed Transmitter
9
St
Differential Pair
C
E
B
F
D
H
G
