Chapter 4: BIOS
SuperServer 5019P-MT/MTR User's Manual
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CPU SLOT2 PCI-E 3.0 X8 / CPU SLOT6 PCI-E X16 / CPU SLOT4
PCI-E X16 / CPU SLOT3 PCI-E X8
Link Speed
Use this item to select the link speed for the PCI-E port specified by the user. The
options are
Auto,
Gen 1 (2.5 GT/s), Gen 2 (5 GT/s), and Gen 3 (8 GT/s).
The following information will also be displayed:
•
PCI-E Port Link Status
•
PCI-E Port Link Max
•
PCI-E Port Link Speed
PCI-E Port Max Payload Size
Selecting
Auto
for this feature will enable the motherboard to automatically detect
the maximum Transaction Layer Packet (TLP) size for the connected PCI-E device,
allowing for maximum I/O efficiency. Selecting 128B or 256B will designate maximum
packet size of 128 or 256. The options are 128B, 256B, and
Auto.
IOAT Configuration
Disable TPH
Transparent Huge Pages (TPH) is a Linux memory management system that enables
communication in larger blocks (pages). Enabling this feature will increase perfor-
mance. The options are
No
and Yes.
Prioritize TPH
Use this feature to enable Prioritize TPH support. The options are Enable and
Disable.
Relaxed Ordering
Select Enable to enable Relaxed Ordering support which will allow certain transactions
to violate the strict-ordering rules of PCI bus for a transaction to be completed prior
to other transactions that have already been enqueued. The options are
Disable
and
Enable.
Patrol Scrub
Patrol Scrubbing is a process that allows the CPU to correct correctable memory errors
detected on a memory module and send the correction to the requestor (the original
source). When this item is set to Enable, the IO hub will read and write back one cache
line every 16K cycles if there is no delay caused by internal processing. By using this
method, roughly 64 GB of memory behind the IO hub will be scrubbed every day. The
options are Disable and
Enable
.
Patrol Scrub Interval
This feature allows you to decide how many hours the system should wait before the
next complete patrol scrub is performed. Use the keyboard to enter a value from 0-24.
The default setting is
24
.
IIO Configuration
EV DFX Features
When this feature is set to Enable, the EV_DFX Lock Bits that are located on a proces-
sor will always remain clear during electric tuning. The options are
Disable
and Enable.
CPU Configuration
IOU0 (II0 PCIe Br1)
This item configures the PCI-E port Bifuraction setting for a PCI-E port specified by the
user. The options are x4x4x4x4, x4x4x8, x8x4x4, x8x8, x16, and
Auto
.
IOU1 (II0 PCIe Br2)
This item configures the PCI-E port Bifuraction setting for a PCI-E port specified by the
user. The options are x4x4x4x4, x4x4x8, x8x4x4, x8x8, x16, and
Auto
.
IOU2 (II0 PCIe Br3)
This item configures the PCI-E port Bifuraction setting for a PCI-E port specified by the
user. The options are x4x4x4x4, x4x4x8, x8x4x4, x8x8, x16, and
Auto
.
