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Chapter 2: Running Setup
DRAM Write Burst Timing
You can define the DRAM write burst timing by setting the DRAM
speed to Manual. This option sets the timing for system memory
burst mode write operations. The settings for this option are
x4EDO/x4FPM, x3EDO/x3FPM, or x2EDO/x2FPM. The Optimal and
Fail-Safe default settings are x4EDO/x4FPM.
DRAM Leadoff Timing (DLT)
You can define the DRAM leadoff timing by setting the DRAM speed
to Manual. This option sets the leadoff timings (Read leadoff/W rite
leadoff/RAS# Precharge). The settings are 11/7/3, 10/6/3, 11/7/4, or
10/6/4. The Optimal and Fail-Safe default settings are 11/7/3.
Speculative Leadoff Timing
When set to Disabled, the DRAM controller read request is pre-
sented before the final memory target is decoded by the MTXC. This
results in a 1 hclk pull-in for all read leadoff latencies. The settings
for this option are Enabled or Disabled. The Optimal and Fail-Safe
default settings are Disabled.
Memory Address Drive Strength
This option controls the strength of the output buffers driving the
MA, MAA, SRAS#, SCAS#, MWE# and CKE pins. The settings for
this option are 10mA/10mA, 10mA/16mA, 16mA/10mA or 16mA/
16mA. The Optimal and Fail-Safe default settings are 10mA/10mA.
Enhanced Paging Disable
When set to Enabled, the MTXC will keep the page open until a
page/row miss. When set to Disabled, the MTXC will use additional
information to keep the DRAM page open when host may be "right
back". The Optimal and Fail-Safe default settings are Enabled.
