Chapter 2: Installation
2-29
JBT1
JP9
T-SGPIO2
T-SGPIO1
BIOS
LICENSE
IPMI CODE
MAC CODE
BAR CODE
JIPMB1
JSD1
SP1
LED3
LED2
JD1
LED5
LED1
BIOS
XDP1
JPI2C1
BT1
JPW1
JTPM1
JF1
FANA
FAN3
FAN1
FAN2
FAN4
JPL4
JPL3
JPL1
JPL2
JPME2
JPG1
JBR1
JPB1
JPME1
J19 J18
JVR1
J22
JI2C1 JI2C2
JOH1
JL1
JP2
JP1
JP7
SLOT4 PCI-X 133/100MHZ
SLOT1 PCI-X 133/100MHZ
SLOT2 PCI-X 133/100MHZ
SLOT3 PCI-X 133/100MHZ
PCH SLOT5 PCI-E 2.0 X1
USB8(3.0)
VGA
LAN2
LAN1
USB2/3 USB0/1
IPMI_LAN
COM2
COM1
DIMMB1
DIMMB2
DIMMA2
DIMMA1
PCH SLOT6 PCI-E 2.0 X4(IN X8)
CPU SLOT7 PCI-E 3.0 X8
JRK1
I-SA
TA5
I-SA
TA4
I-SA
TA0
I-SA
TA3
I-SA
TA2
I-SA
TA1
USB5/6
CPU
J7
JWD1
IPMI
LED4
JSTBY1
USB7(3.0)
USB4
FP
CTRL
JPW2
X10SLX-F
Rev
.1.00
Intel PXH
Intel PCH
BMC
LAN
CTRL
LAN
CTRL
SW1
A
A. TPM/Port 80
TPM Header/Port 80 Header
A Trusted Platform Module/Port 80
header, located at JTPM1, provides
TPM/Port 80 support to enhance
system performance and data secu-
rity. See the table on the right for pin
definitions.
TPM/Port 80 Header
Pin Definitions
Pin # Definition
Pin # Definition
1
LCLK
2
GND
3
LFRAME#
4
<(KEY)>
5
LRESET#
6
+5V (X)
7
LAD 3
8
LAD 2
9
+3.3V
10
LAD1
11
LAD0
12
GND
13
SMB_CLK4
14
SMB_DAT4
15
+3V_DUAL
16
SERIRQ
17
GND
18
CLKRUN# (X)
19
LPCPD#
20
LDRQ# (X)