Version 1.0
Page 35 of 44
SMT370v2 User Manual
Direct Transfer: When Direct To DAC mode selected, data are written into a FIFO (that can contain up
to 512 words of 16 bits) under the SHB clock and sent out to the DAC directly under the DAC
sampling clock. Every data received on the SHB is passed to the DAC. This mode works with either
two 16-bit interfaces or one 32-bit interface. In the first case, as both 16-bit data flows are not
necessarily synchronised, they ‘wait’ for each other. It is possible to check that this mode is selected
by looking at LED3 that should be ON.
Pattern Generator: In that mode, the idea is to load a pattern or a buffer of data (of size ‘Pattern Size)
describing one or an entire number of periods into the on-board memory and get the FPGA to read it
back continuously and send the data to the DAC at the DAC sampling rate. ‘Pattern Size’ describes
the number of data that the FPGA expects to receive when sending the pattern and the size to read
back continuously.
Start/Stop: This to start or stop the pattern generator, i.e. the read back operation. Make sure that a
Start operation is not selected when loading data into memory for pattern use. Data are written into the
memory under the SHB clock and read out under the DAC sampling clock.
