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Sundance Spas SMT370v2, User Manual

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Sundance Spas SMT370v2 User Manual Download Page 37

Version 1.0 

Page 37 of 44

 

SMT370v2 User Manual 

 

Register 0xF – Serial Interfaces load. 

The DAC and the clock synthesizers have all a 

S

erial 

P

ort 

I

nterface. By sending this 

control word, the FPGA serialises Register 0 to 5 and send them to the DAC and 
both clock synthesizers. 

Bit 

number 

Description 

Bit 31 

1 

Bit 30 

1 

Bit 29 

1 

Bit 28 

1 

Bit 27-0 

Not Used. 

Summary of Contents for SMT370v2

Page 1: ...SMT370v2 User Manual User Manual QCF42 Version 3 0 8 11 00 Sundance Multiprocessor Technology Ltd 1999...

Page 2: ...Date Comments Engineer Version 14 02 03 First release PSR 1 0 08 03 03 Details added about registers and external signals figure references examples PSR 1 1 31 03 03 FPGA Firmware changed ADC DAC Trig...

Page 3: ...PGA 9 Communication Ports CommPorts 9 SHB 10 Memory 10 Clock management 11 TTL I Os 11 External triggering 11 ADCs and DAC 11 LEDs 12 Sundance Standards 12 Communication Ports 12 Sundance High speed B...

Page 4: ...agement 31 Register 0x6 Channel selection Triggers Decimator 33 Register 0x7 DAC control Pattern generator 34 Register 0xE DAC Register Read back 36 Register 0xF Serial Interfaces load 37 Example code...

Page 5: ...ort following the TI C4x standards Precautions In order to guarantee that the SMT370 functions correctly and to protect the module from damage the following precautions should be taken The SMT370 is a...

Page 6: ...width module Two Sundance High speed Bus SHB connectors Two 20 MegaByte s communication ports Low jitter on board system clock Xilinx Virtex II FPGA 50 Ohm terminated analogue inputs and outputs exte...

Page 7: ...LQFP 30 I O pins 28 bit data ctl 1x AD9777 DAC 16 bit 400MSPS 80 pin TQFP 44 I O pins 16 bit data ctl 4 3 RF transformer 2 Clock feedback Trig 1 Trig 2 6 pin JTAG header On board Oscillator 50 MHz 4...

Page 8: ...ect both ADCs and the DAC to the FPGA which is responsible for transferring samples from to the converters An on board frequency synthesizer generates differential encode lines sampling clocks to feed...

Page 9: ...riggers have clamping diodes to 3 3V and to Ground to avoid damaging the FPGA they are connected to A global reset signal is mapped to the FPGA from the top TIM connector to reset the FPGA and reload...

Page 10: ...ata stream goes through a Decimator which value 0 to 31 can be set in a control register Both decimators are independent If both decimators are set with the same values and if the sampling clocks for...

Page 11: ...made via the control register TTL I Os Four TTL I Os J6 see Figure 9 Connector Location are connected directly to the FPGA They support LVTTL signals It is recommended to make sure the lines connected...

Page 12: ...dicated when the FPGA is not programme In normal operation i e J8 fitted Figure 9 Connector Location it flashes once at power up and after a module reset Sundance Standards Communication Ports CommPor...

Page 13: ...e FPGA D 0 31 FIFO 256x32x2 D 0 15 Control LogicandStatus CLK W EN REQ ACK SHB A DATA Figure 3 SHB interface structure SMT370 communication links The SMT370 provides 2 CommPort links They are given th...

Page 14: ...aliasing filter External Clock Minimum voltage 0 2 Volt peak to peak minimum Impedance 50 Frequency range 30 105 MHz low jitter External Trigger Frequency Range 30 105 MHz Signal format LVTTL 3 3 Vol...

Page 15: ...he board The test has been performed without any input filter which explains the second peak due to harmonics at all and with a 35dBc harmonic performance signal generator Figure 5 FFT ADC Channel On...

Page 16: ...inimum voltage 0 2 Volt peak to peak minimum Impedance 50 Frequency range 20 160 MHz low jitter External Trigger Frequency Range 30 160 MHz Signal format LVTTL 3 3 Volts format connected to 3 3V FPGA...

Page 17: ...17 of 44 SMT370v2 User Manual The following capture shows a 5MHz signal generated by the DAC under an on board sampling clock of 160MHz Note that no output filter was used during the capture Figure 7...

Page 18: ...32 D30 52 D50 13 D11 CLK1 33 D31 53 D51 14 D12 34 D32 WEN2 54 D52 15 D13 35 D33 REQ2 55 D53 16 D14 36 D34 ACK2 56 D54 17 D15 37 D35 CLK3 57 D55 18 D16 38 D36 58 D56 WEN4 19 D17 39 D37 59 D57 REQ4 20...

Page 19: ...Q_CLK_SEL_DAC 1 LOC E17 NET FREQ_CLK_SEL 0 LOC D21 NET FREQ_nP_LOAD_ADCs LOC B18 NET FREQ_nP_LOAD_DAC LOC D17 NET FREQ_S_CLOCK_ADCs LOC A19 NET FREQ_S_CLOCK_DAC LOC A17 NET FREQ_S_DATA_ADCs LOC B19 NE...

Page 20: ...DQa 7 LOC A8 NET ZBT_DQa 6 LOC B8 NET ZBT_DQa 5 LOC F9 NET ZBT_DQa 4 LOC E9 NET ZBT_DQa 3 LOC C9 NET ZBT_DQa 2 LOC D9 NET ZBT_DQa 1 LOC A9 NET ZBT_DQa 0 LOC B9 NET ZBT_CS2 LOC B13 NET ZBT_CLK LOC B11...

Page 21: ...C_P1B 8 LOC W18 NET DAC_P1B 9 LOC Y18 NET DAC_P1B 10 LOC AB19 NET DAC_P1B 11 LOC V17 NET DAC_P1B 12 LOC AA20 NET DAC_P1B 13 LOC W20 NET DAC_P1B 14 LOC Y21 NET DAC_P1B 15 LOC Y22 NET DAC_P2B 0 LOC W13...

Page 22: ...C E21 NET SHBB 2 LOC E20 NET SHBB 1 LOC E19 NET SHBB 0 LOC D22 NET SHBA 59 LOC W2 NET SHBA 58 LOC W1 NET SHBA 57 LOC U4 NET SHBA 56 LOC U3 NET SHBA 55 LOC V2 NET SHBA 54 LOC V1 NET SHBA 53 LOC U2 NET...

Page 23: ...LOC H5 NET SHBA 1 LOC G1 NET SHBA 0 LOC G2 At power up and on reset At power up the FPGA is not configured and is waiting for a bit stream to be loaded By fitting Jumper J8 Figure 9 Connector Locatio...

Page 24: ...Version 1 0 Page 24 of 44 SMT370v2 User Manual Connector position Figure 9 Connector Location The diagram below gives the position and the meaning of the connectors that the customer is likely to use...

Page 25: ...ecified in the TIM specification these new generation modules require an additional 3 3v supply to be presented on the two diagonally opposite TIM mounting holes The lack of this 3 3v power supply sho...

Page 26: ...or only on read back Bit 16 Not Used Bit 15 Filter interpolation rate Bit 1 1x 2x 4x or 8x Bit 14 Filter interpolation rate Bit 0 1x 2x 4x or 8x Bit 13 Modulation mode Bit 1 None fs 2 fs 4 or fs 8 Bit...

Page 27: ...L Off or 1 PLL on when using modulation Bit 14 0 Automatic Charge Pump Control or 1 Programmable Bit 13 Bit 12 Bit 11 Not Used Bit 10 PLL Charge Pump Control Bit 9 PLL Charge Pump Control Bit 8 PLL Ch...

Page 28: ...Gain Adjustment Bit 16 IDAC Coarse Gain Adjustment Bit 15 IDAC Offset Adjustment Bit9 Bit 14 IDAC Offset Adjustment Bit8 Bit 13 IDAC Offset Adjustment Bit7 Bit 12 IDAC Offset Adjustment Bit6 Bit 11 ID...

Page 29: ...Gain Adjustment Bit 18 QDAC Fine Gain Adjustment Bit 17 QDAC Fine Gain Adjustment Bit 16 QDAC Fine Gain Adjustment Bit 15 12 Not Used Bit 11 QDAC Coarse Gain Adjustment Bit 10 QDAC Coarse Gain Adjustm...

Page 30: ...1 Bit 29 0 Bit 28 0 Bit 27 24 Not Used Bit 23 QDAC IOFFSET Direction 0 IOFFSET on IOUTA or 1 IOFFSET on IOUTB Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Not Used Bit 17 QDAC Offset Adjustment Bit1 Bit 16 QDA...

Page 31: ...Bit 19 Clock synthesizer M Bit7 ADCs Bit 18 Clock synthesizer M Bit6 ADCs Bit 17 Clock synthesizer M Bit5 ADCs Bit 16 Clock synthesizer M Bit4 ADCs Bit 15 Clock synthesizer M Bit3 ADCs Bit 14 Clock s...

Page 32: ...signals can be routed on the board A and B Xilinx FPGA Virtex II FG456 XC2V1000 6 324 I O Pins 1 5V Core 3 3V I O 1 AC or DC coupling 2xAD6645 ADCs 14 bit 105MSPS 52 pin LQFP 30 I O pins 28 bit data...

Page 33: ...cimation Factor Channel B Bit 2 Bit 21 Decimation Factor Channel B Bit 1 Bit 20 Decimation Factor Channel B Bit 0 Bit 17 19 Bit 16 Decimation Factor Channel A Bit 4 Bit 15 Decimation Factor Channel A...

Page 34: ...To DAC mode 0 Pattern generator mode Bit 21 Start Stop Pattern generator 1 Start 0 Stop Bit 20 Load Pattern Size Active high 1 Load into FPGA 0 No Load Bit 19 Pattern Size Bit 19 Bit 18 Pattern Size...

Page 35: ...ted by looking at LED3 that should be ON Pattern Generator In that mode the idea is to load a pattern or a buffer of data of size Pattern Size describing one or an entire number of periods into the on...

Page 36: ...on up to register 0xd Example Let s consider that the following registers have been loaded into the DAC Register0 0x00010203 Register1 0x01111213 Register2 0x02212223 Register3 0x03313233 Register4 0...

Page 37: ...aces load The DAC and the clock synthesizers have all a Serial Port Interface By sending this control word the FPGA serialises Register 0 to 5 and send them to the DAC and both clock synthesizers Bit...

Page 38: ...00 Reg 3 QDAC Fine Gain 0xFF Reg 3 QDAC Coarse Gain 0xF define REGISTER_4 0x40000000 define REGISTER_5 0x50990D90 Reg5 On board clocks selected for ADCs and DAC Reg5 ADCs on board clk 100 MHz 0x990 M...

Page 39: ...im 2 SMT_SDB Sdb3 SMT_SDB_Claim 3 verifying that allocation OK if BufferA printf Cannot allocate BufferA n exit 1 if BufferB printf Cannot allocate BufferB n exit 1 if BufferC printf Cannot allocate B...

Page 40: ...ar input fifo prior to read operation SMT_SDB_Read Sdb0 4 DATA_SIZE BufferC size in byte SMT_SDB_Control Sdb1 SDB_CLRIF Clear input fifo prior to read operation SMT_SDB_Read Sdb1 4 DATA_SIZE BufferD s...

Page 41: ...000400 Reg 0 Real data define REGISTER_1 0x100000ff Reg 1 IDAC Fine Gain 0xFF define REGISTER_2 0x200f0000 Reg 2 IDAC Coarse gain 0xF define REGISTER_3 0x30ff0f00 Reg 3 QDAC Fine Gain 0xFF Reg 3 QDAC...

Page 42: ...int BufferB memalign 128 4 PATTERN_SIZE size in bytes aligns address to 128 necessary for SMT_SDB_Read function int BufferC memalign 128 4 PATTERN_SIZE int BufferD memalign 128 4 PATTERN_SIZE Claiming...

Page 43: ...EGISTER_E COMM_PORT0 index 0 printf Waiting for words n printf CP0 status 08x n SMT365CP0_STAT while SMT365CP0_STAT CP0_STAT_IFE 0x00000000 link_in_word ReadBackWord COMM_PORT0 printf CP0 status 08x t...

Page 44: ...Capturing data from ADCs n SMT_SDB_Control Sdb0 SDB_CLRIF Clear input fifo prior to read operation SMT_SDB_Read Sdb0 4 PATTERN_SIZE BufferC size in byte SMT_SDB_Control Sdb1 SDB_CLRIF Clear input fif...

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