User Guide FMC-DAQ2p5
Page 6 of 19
Rev. 1.0
PROPRIETARY NOTICE:
The information contained herein is proprietary to Sundance DSP Inc., and shall not be reproduced or disclosed in whole or
in part, or used for any other design or manufacture without written authorization from Sundance DSP Inc.
External trigger input on this module allows users to add a time stamps on the sample stream
from ADC.
CLK IN interface can be a Sample clock input up to 4GHz, or reference clock input up to 1GHz.
Board clocking structure provides the possibility of deterministic latency and subclass 1
synchronization.
Simultaneous operation of ADC and DAC is supported at a sample rate of 2.1GSPS, using
internal VCXO clock. In this case clocks from 2.1GHz clocks from HMC7044 goes to ADC and
DAC. This IC also provides SYSREF clock with known and adjustable delay. Per JESD204B,
REF and SYSREF CLK are provided to FPGA to achieve requirement of subclass 1 JESD204B.
Figure 2: Simplified FMC-DAQ2p5 board Block Diagram
In the FPGA, REF CLK can be used to clock TX and RX paths. Inside the FPGA transceivers
there are two PLLs. One QPLL
– common for four transceivers (called quad), and CPLL – one
for each transceiver. These provide possibility to run Rx and Tx channels at different rates. For
more information see
PG066-JESD204.pdf
from Xilinx. See sections on Sharing Transceivers
between Transmit and Receive.
