User Guide FMC-DAQ2p5
Page 7 of 19
Rev. 1.0
PROPRIETARY NOTICE:
The information contained herein is proprietary to Sundance DSP Inc., and shall not be reproduced or disclosed in whole or
in part, or used for any other design or manufacture without written authorization from Sundance DSP Inc.
3 C
LOCK PROGRAMMING GUIDE
To achieve maximum data throughput from ADC and DAC during simultaneous
operation, user must program the clock chips as detailed below.
HMC7044 VCO frequency must be set to 2.6GHz. Device clock to ADC must be set to
2.6GHz, setting channel divider to 1.
Per ADC datasheet line rate will be 2*Fs = 5.2 Gb/s and using 8 lanes. This requires a 5200/40
= 130 MHz clock for JESD204 Rx core, this can be achieved by programming output channel
divider to 20.
Device Clock to DAC must be 260MHz, this is achieved by programming channel divider in the
HMC7044 to 10. Inside DAC you must turn on DAC PLL, and set following parameters:
RefDivFactor = 4(REF_DIV_MODE register = 2), LODivFactor = 4(LO_DIV_MODE register = 1),
BCount = 16. This give us DAC sample rate of 2080 MHz and 10.4Gb/s Lane rate with 8 lanes.
This requires 10400/40 = 260 MHz for JESD Tx Core, and is achieved by programming output
channel divider of HMC7044 to 10.
This is the proposed method for achieving 2.6GSPS for ADC and 2.08GSPS for DAC. Many
other combinations of frequencies are available and please see datasheet in the references.
3.1 Programming to maximum rates with PXIe_700 board.
A complete Viv
ado project using this module with Sundance DSP’s PXIe700 is provided to
kick start the development. For using the module on the PXI700 the HMC7044 VCO frequency
must be set to 2.6GHz. Device clock to ADC must be set to 2.6GHz, setting channel divider to
1.
According to ADC datasheet line rate will be 2*Fs = 5.2 Gb/s and using 8 lanes. This requires a
5200/40 = 130 MHz clock for JESD204 Rx core, this can be achieved by programming output
channel divider to 20.
Device Clock to DAC must be set to 260MHz, and this is achieved by programming channel
divider in the HMC7044 to 10. Inside DAC you must turn on DAC PLL, and set following
parameters: RefDivFactor = 4(REF_DIV_MODE register = 2), LODivFactor = 4(LO_DIV_MODE
register = 1), BCount = 10. This give us DAC sample rate 1300 MHz and 6.5Gb/s Lane rate with
8 lanes. This requires 6500/40 = 162.5 MHz for JESD Tx Core, and is achieved by
programming output channel divider of HMC7044 to 16.
By using the above settings 2.6GSP/S for ADC and 1.33GSP/S for DAC is achieved. Again,
there are a lot of other combinations of available frequencies which can be achieved by
changing the settings.
4 M
AIN PARAMETERS OF THE
FMC-DAQ2
P
5
BOARD
4.1 ADC part parameters
12-Bit Resolution, single-Chanel, 2.7-GSPS ADC
Noise Floor:
–146 dBFS/Hz
