Appendix A
Configuring BIOS and POST
A-41
8E
Programs the peripheral parameters. Enable/Disable NMI as selected.
90
Late POST initialization of system management interrupt.
A0
Checks boot password if installed.
A1
Clean-up work needed before booting to OS.
A2
Takes care of runtime image preparation for different BIOS modules. Fills the free area in
F000h segment with 0FFh. Initializes the Microsoft IRQ routing table. Prepares the runtime
language module. Disables the system configuration display if needed.
A4
Initializes runtime language module.
A7
Displays the system configuration screen if enabled. Initializes the CPUs before boot,
which includes the programming of the MTRRs.
A8
Prepares CPU for OS boot including final MTRR values.
A9
Waits for user input at config display if needed.
AA
Uninstalls POST INT1Ch vector and INT09h vector. Deinitializes the ADM module.
AB
Prepares BBS for Int 19 boot.
AC
Any kind of chipsets (NB/SB) specific programming needed during End- POST, just
before giving control to runtime code booting to OS. Programmed the system BIOS
(0F0000h shadow RAM) cacheability. Ported to handle any OEM specific programming
needed during End-POST. Copies OEM specific data from POST_DSEG to RUN_CSEG.
B1
Saves system context for ACPI.
00
Prepares CPU for booting to OS by copying all of the context of the BSP to all application
processors present. Note: APs are left in the CLIHLT state.
61-70
OEM POST error. This range is reserved for chipset vendors and system manufacturers.
The error associated with this value might be different from one platform to the next.
TABLE A-4
POST Code Checkpoints
(Continued)
Post Code
Description
