DocID018909 Rev 11
RM0090
Flexible static memory controller (FSMC)
1588
36.6
NAND Flash/PC Card controller
The FSMC generates the appropriate signal timings to drive the following types of device:
•
NAND Flash
–
8-bit
–
16-bit
•
16-bit PC Card compatible devices
The NAND/PC Card controller can control three external banks. Bank 2 and bank 3 support
NAND Flash devices. Bank 4 supports PC Card devices.
Each bank is configured by means of dedicated registers (
). The
programmable memory parameters include access timings (shown in
) and ECC
configuration.
Bits 15:8
DATAST[7:0]:
Data-phase duration.
These bits are written by software to define the duration of the data phase (refer to
to
), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses:
0000 0000: Reserved
0000 0001: DATAST phase duration = 1 × HCLK clock cycles
0000 0010: DATAST phase duration = 2 × HCLK clock cycles
...
1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)
Note: In synchronous accesses, this value is don't care.
Bits 7:4
ADDHLD[3:0]:
Address-hold phase duration.
These bits are written by software to define the duration of the
address hold
phase (refer to
to
), used in asynchronous multiplexed accesses:
0000: Reserved
0001: ADDHLD phase duration = 1 × HCLK clock cycle
0010: ADDHLD phase duration = 2 × HCLK clock cycle
...
1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)
Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always
1 Flash clock period duration.
Bits 3:0
ADDSET[3:0]:
Address setup phase duration.
These bits are written by software to define the duration of the
address setup
phase in HCLK cycles
(refer to
), used in asynchronous accessed:
0000: ADDSET phase duration = 0 × HCLK clock cycle
...
1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset)
Note: In synchronous NOR Flash and PSRAM accesses, this value is don’t care.
