Stanford Research Systems SIM918, Operating And Service Manual

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3 – 24 Remote Operation
3.5 Status Model
The SIM918 status registers follow the hierarchical IEEE–488.2 for-
status registers
mat. A block diagram of the status register array is given in Figure 3.1.
7
X
5
4
3
2
1
0
CESB
MSS
ESB
IDLE
undef
undef
RCSB
OLSB
7
6
5
4
3
2
1
0
Status Byte
SB SRE
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
OPC: Operation Complete
INP: Input Buffer Error
DDE: Device Error
EXE: Execution Error
CME: Command Error
URQ: User Request
PON: Power On
QYE: Query Error
ESR ESE
Standard Event Status
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
PARITY: Parity Error
FRAME: Framing Error
HWOVRN: Hardware Input Overrun
OVR: Input Buffer Overrun
RTSH: RTS Halted
CTSH: CTS Halted
DCAS: Device Clear
NOISE: Noise Error
CESR CESE
Communication Error Status
X
X
X
X
X
2
1
0
X
X
X
X
X
2
1
0 Bias
Output
undef
undef
undef
undef
undef
Bias + Output
OLSR OLSE
Overload Status
-STATUS
X
X
X
X
3
2
1
0
X
X
X
X
3
2
1
0
Leave
Arrive
Lock
undef
undef
undef
undef
Unlock
RCSR RCSE
Reference Clock Status
Figure 3.1: Status register model for the SIM918 Precision Cur-
rent Preamplifier.
There are two categories of registers in the SIM918 status model:
Event Registers : These read-only registers record the occurrence of defined
events. If the event occurs, the corresponding bit is set to 1.
Upon querying an event register, all set bits within it are
cleared. These are sometimes known as “sticky bits,” since
once set, a bit can only be cleared by reading its value. Event
register names end with SR.
Enable Registers : These read
/
write registers define a bitwise mask for their cor-
responding event register. If a bit position is set in an event
register while the same bit position is also set in the enable
register, then the corresponding summary bit message is set.
Enable register names end with SE.
SIM918 Precision Current Preamplifier