Stanford Research Systems SIM918, Operating And Service Manual

Page: 60 / 68

3 – 28 Remote Operation
Weight Bit Flag
1 0 Bias
2 1 Output
4 2 Bias
+
Output
8 3 undef (0)
16 4 undef (0)
32 5 undef (0)
64 6 undef (0)
128 7 undef (0)
Bias : Bias overload. Indicates that
| V
bias
|
>
5
.
0 V (see also Sec-
tion 1.2.4.1).
Output : Output overload. Indicates that | V
out
|
>
10
.
0 V (see also Sec-
tion 1.2.5).
Bias
+
Output : Transimpedance stage overload. Indicates that
| V
bias
− i
in
× R
F
|
>
10
.
0 V
.
Reading this register (with the OLSR? query) clears all overload bits
that are set. If the overload condition persists, the bits will remain
cleared until the overload condition ceases and reoccurs. Use
OVLD?
to query the current state of the overload.
3.5.8 Overload Status Enable (OLSE)
The OLSE acts as a bitwise AND with the OLSR register to produce
the single-bit OLSB message in the Status Byte Register (SB). The
register can be set and queried with the
OLSE(?) command.
At power-on, this register is cleared.
3.5.9 Reference Clock Status (RCSR)
The Reference Clock Status Register consists of 4 event flags; each of
the flags is set by the corresponding clock event, and cleared only by
reading the register or with the
*CLS command. Reading a single bit
(with the RCSR? i query) clears only Bit i .
Weight Bit Flag
1 0 Leave
2 1 Arrive
4 2 Unlock
8 3 Lock
16 4 undef (0)
32 5 undef (0)
64 6 undef (0)
128 7 undef (0)
Leave : Reference clock stop detect. Indicates that the external refer-
ence clock signal has ceased.
SIM918 Precision Current Preamplifier