AN4488 Rev 7
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AN4488
Power supplies
49
2.2 Power
supply
schemes
The circuit is powered by a stabilized power supply, V
DD
.
Caution:
The V
DD
voltage range is 1.8 V to 3.6 V (down to 1.7 V with some restrictions, see relative
Datasheet for details).
•
The V
DD
pins must be connected to V
DD
with external decoupling capacitors: one
single Tantalum or Ceramic capacitor (min. 4.7 µF typ.10 µF) for the p one
100 nF Ceramic capacitor for each V
DD
pin.
•
The V
BAT
pin can be connected to the external battery (1.65 V < V
BAT
< 3.6 V). If no
external battery is used, it is recommended to connect this pin to V
DD
with a 100 nF
external ceramic decoupling capacitor.
•
The V
DDA
pin must be connected to two external decoupling capacitors (100 nF
C 1 µF Tantalum or Ceramic).
•
The V
REF+
pin can be connected to the V
DDA
external power supply. If a separate,
external reference voltage is applied on V
REF+
, a 100 nF and a 1 µF capacitors must
be connected on this pin. In all cases, V
REF+
must be kept between (V
DDA
-1.2 V) and
V
DDA
with minimum of 1.7 V.
•
Additional precautions can be taken to filter analog noise:
–
V
DDA
can be connected to V
DD
through a ferrite bead.
–
The V
REF+
pin can be connected to V
DDA
through a resistor.
•
For the voltage regulator configuration, there is specific BYPASS_REG pin (not
available on all packages) that should be connected either to V
SS
or V
DD
to activate or
deactivate the voltage regulator specific.
–
and section "Voltage regulator" of the related device
datasheet for details
.
•
When the voltage regulator is enabled, V
CAP1
and V
CAP2
pins must be connected to
2*2.2 µF LowESR < 2
Ω
Ceramic capacitor (or 1*4.7 µF LowESR < 1
Ω
Ceramic
capacitor if only V
CAP1
pin is provided on some packages).
