Power supplies
AN4488
8/50
AN4488 Rev 7
PA0 pin should be used for this purpose, and act as power-on reset on V12 power
domain.
•
In regulator OFF mode, the following features are no more supported:
–
PA0 cannot be used as a GPIO pin since it allows to reset a part of the V12 logic
power domain which is not reset by the NRST pin.
–
As long as PA0 is kept low, the debug mode cannot be used under power-on
reset. As a consequence, PA0 and NRST pins must be managed separately if the
debug connection under reset or pre-reset is required.
–
The over-drive and under-drive modes are not available.
–
The Standby mode is not available.
Figure 1. BYPASS_REG supervisor reset connection
1. V
CAP2
is not available on all packages. In that case, a single 100 nF decoupling capacitor is connected to
V
CAP1
The following conditions must be respected:
•
V
DD
should always be higher than V
CAP
to avoid current injection between power
domains.
•
If the time for V
CAP
to reach V12 minimum value is smaller than the time for V
DD
to
reach 1.7 V, then PA0 should be kept low to cover both conditions: until V
CAP
reaches
V12 minimum value and until V
DD
reaches 1.7 V.
•
Otherwise, if the time for V
CAP
to reach V12 minimum value is smaller than the time for
V
DD
to reach 1.7 V, then PA0 could be asserted low externally.
•
If V
CAP
goes below V12 minimum value and V
DD
is higher than 1.7 V, then PA0 must
be asserted low externally.
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