STA382BW
Register description: New Map
Doc ID 022783 Rev 1
6.30.3
Channel PWM enable (CPWMEN) bit
This bit, when set, activates a mute output in case the volume reaches a value lower
than -76 dBFS.
6.30.4 External
amplifier
hardware
pin enabler (LPDP, LPD LPDE) bits
Pin 42 (INTLINE), normally indicating a fault condition, using the following 3 register settings
can be reconfigured as a hardware pin enabler for an external headphone or line amplifier.
In particular the LPDE bit, when set, activates this function. Accordingly, the LPD value (0 or
1) is exported on pin 42 and in case of power-down assertion, pin 42 is tied to LPDP.
The LPDP bit, when set, negates the value programmed as the LPD value, refer to the
following table.
Table 87.
External amplifier enabler configuration bits
Figure 27.
Alternate function for INTLINE pin
6.30.5
Power-down delay selector (PNDLSL[2:0]) bits
The assertion of PWDN activates a counter that, by default, after 13 million clock cycles
puts the power bridge in tristate mode, independently from the fade-out time. Using these
registers it is possible to program this counter according to the following table.
LPDP
LPD
LPDE
Pin 42 output
x
x
0
INT_LINE
0
0
1
0
0
1
1
1
1
0
1
1
1
1
1
0
Y
N
‘0 ’
L P D
“is th e d evice in p ow erd o w n ?”
0
1
L P D P
0
1
L P D E
P o w er B rid ge Fau lt
IN T L IN E
Obsolete Product(s) - Obsolete Product(s)
