ST Sound Termina STA382BWTR Manual Download Page 50

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Register description: New Map

STA382BW

50/172

Doc ID 022783 Rev 1

6.9

POST scaler register (addr 0x08)

Post scaler is set to POST/128 for both CH1 and CH2.

6.10

OPER register (addr 0x09)

POST[7:0]

Reserved

OPER[1:0]

Table 23.

OPER register

Bit

R/W

RST

Name

Description

R/W

OPER[1:0]

output configuration modes

R/W

Table 24.

OPER configuration selection

OPER[1:0]

Output configuration

PBTL enable

2-channel (full-bridge) power, 2-channel data-out:

1A/1B

→

1A/1B

2A/2B

→

2A/2B

LineOut1

→

3A/3B

LineOut2

→

4A/4B

Line out configuration determined by LOC register

2-channel (full-bridge) power, 1-channel FFX:

1A/1B

→

1A/1B

2A/2B

→

2A/2B

3A/3B

→

3A/3B

EAPDEXT and TWARNEXT Active

Yes

2(half-bridge).1(full-bridge) on-board power:

→

1A Binary 0°

→

1B Binary 90°

3A/3B

→

2A/2B Binary 45°

1A/B

→

3A/B Binary 0°

2A/B

→

4A/B Binary 90°

1 channel mono-parallel:

→

1A/1B w/ C3BO 45°

→

2A/2B w/ C3BO 45°

1A/1B

→

3A/3B

2A/2B

→

4A/4B

CH3 downmixed on all the PWM channels.

Obsolete Product(s) - Obsolete Product(s)

Summary of Contents for Sound Termina STA382BWTR

Page 1: ...ampling frequency Embedded RMS meter for measuring real time loudness Two analog outputs Selectable headphone line out driver with adjustable gain via external resistors New F3XTM analog output New fu...

Page 2: ...al specifications for the power section 24 3 6 Electrical specifications for the analog section 25 4 Device overview 26 4 1 Processing data path 26 4 2 Input oversampling 29 4 3 STCompressorTM 29 4 3...

Page 3: ...egister addr 0x00 46 6 2 STATUS register addr 0x01 46 6 3 RESET register addr 0x02 47 6 4 Soft volume register addr 0x03 47 6 5 MVOL register addr 0x04 48 6 6 FINEVOL register addr 0x05 48 6 7 CH1VOL...

Page 4: ...figuration register F addr 0x16 66 6 18 1 Invalid input detect mute enable 66 6 18 2 Binary output mode clock loss detection 66 6 18 3 LRCK double trigger protection 67 6 18 4 Auto EAPD on clock loss...

Page 5: ...data register bits 15 8 79 6 24 4 Coefficient b1 data register bits 7 0 79 6 24 5 Coefficient b2 data register bits 23 16 80 6 24 6 Coefficient b2 data register bits 15 8 80 6 24 7 Coefficient b2 data...

Page 6: ...el measurement address 0x61 0x65 0x3F 0x40 0x6F 95 6 33 Headphone Line out configuration register address 0x66 97 6 34 F3XCFG address 0x69 0x6A 98 6 35 STCompressorTM configuration register address 0x...

Page 7: ...ble trigger protection 122 7 6 5 Auto EAPD on clock loss 122 7 6 6 IC power down 122 7 6 7 External amplifier power down 123 7 7 Volume control registers addr 0x06 0x0A 123 7 7 1 Mute line output conf...

Page 8: ...ter bits 7 0 135 7 12 5 Coefficient b2 data register bits 23 16 136 7 12 6 Coefficient b2 data register bits 15 8 136 7 12 7 Coefficient b2 data register bits 7 0 136 7 12 8 Coefficient a1 data regist...

Page 9: ...t address 0x4B bit D2 153 7 22 4 External amplifier hardware pin enabler LPDP LPD LPDE bits address 0x4C bit D7 D6 D5 153 7 22 5 Power down delay selector PNDLSL 2 0 bits address 0x4C bit D4 D3 D2 154...

Page 10: ...Contents STA382BW 10 172 Doc ID 022783 Rev 1 10 Revision history 171 Obsolete Product s Obsolete Product s...

Page 11: ...Channel 2 volume register 49 Table 23 OPER register 50 Table 24 OPER configuration selection 50 Table 25 FUNCT register 56 Table 26 HPCFG register 58 Table 27 Master clock select 58 Table 28 Input sam...

Page 12: ...d as a function of LxRT bits AC mode 77 Table 72 Limiter attack threshold as a function of LxAT bits DRC mode 78 Table 73 Limiter release threshold as a function of LxRT bits DRC mode 78 Table 74 RAM...

Page 13: ...t detect mute enable 122 Table 128 Binary output mode clock loss detection 122 Table 129 LRCK double trigger protection 122 Table 130 Auto EAPD on clock loss 122 Table 131 IC power down 122 Table 132...

Page 14: ...149 Table 167 PLL register 0x43 bits 149 Table 168 PLL register 0x44 bits 149 Table 169 PLL register 0x45 bits 150 Table 170 PLL register 0x46 bits 150 Table 171 Coefficients extended range configura...

Page 15: ...6 Figure 25 Basic limiter and volume flow diagram 76 Figure 26 Short circuit detection timing diagram no short detected 91 Figure 27 Alternate function for INTLINE pin 93 Figure 28 Coefficients direct...

Page 16: ...List of figures STA382BW 16 172 Doc ID 022783 Rev 1 Figure 49 VQFN48 7 x 7 x 0 9 mm package outline 169 Obsolete Product s Obsolete Product s...

Page 17: ...different modes A 2 1 channel setup can be implemented with two half bridges L R together with a single full bridge subwoofer Alternatively the 2 0 channel setup can be done with two full bridges Whe...

Page 18: ...N FFX4A GND_REG SOFT_MUTE 2 x GND 2 x VCC VDD_REG GNDPSUB 2 x VDDDIG 2 x GNDDIG VREGFILT AGNDPLL VCC_REG VSS_REG CPM 2 1 Channel Audio Processor STAudioFxTM STSpeakerSafeTM Parametric EQ Volume Bass a...

Page 19: ...VCC2 OUT2A OUT1B VCC1 GND1 OUT1A VDD_REG GND_REG MCLK AGNDPLL VREGFILT TWARN FFX4A EAPD FFX4B FFX3B FFX3A GNDDIG1 VDDDIG1 VDD3V3CHP CPP GNDPSUB 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42...

Page 20: ...3X reference voltage 14 F3XL OUTPUT F3X analog out left channel 15 F3XR OUTPUT F3X analog out right channel 16 LINEINL INPUT Line in left channel 17 LINEINR INPUT Line in right channel 18 LINEHPOUT_L...

Page 21: ...t clock 39 SDI INPUT IIS serial data input 40 RESET INPUT Reset 41 PWDN INPUT Device power down 0 power down 1 normal operation 42 INTLINE OUTPUT Fault interrupt 43 SDA I O IIC serial data 44 SCL INPU...

Page 22: ...current is sunk amplifier in mute state In this case the reliability of the device is guaranteed provided that the absolute maximum ratings are not exceeded 3 2 Thermal data Table 3 Absolute maximum r...

Page 23: ...O supply 2 7 3 3 3 6 V Tamb Ambient temperature 0 70 C RLine Load impedance line driver mode 5 10 k RHp Load impedance headphone driver mode 16 32 RBtl Load impedance power output BTL mode 5 8 Table 6...

Page 24: ...istive load 2 8 15 ns tr Rise time Resistive load 2 10 18 ns tf Fall time Resistive load 2 10 18 ns Ivcc Supply current from Vcc in power down PWRDN 0 0 1 1 A Supply current from Vcc in operation PCM...

Page 25: ...line out Gv 2 5 THD 1 Rload 5 k 1 9 2 1 Vrms Pout Output voltage for HP out THD N 10 Gv 2 5 Rload 32 40 mW DR Dynamic range for line out Vout 2 VRMS Fin 200 Hz Vin 0 8 mV 60 dBFs 100 dB X Talk Channel...

Page 26: ...ers per channel are enabled plus the pre configured Bass and Treble controls BQL 0 BQ5 0 BQ6 0 BQ7 0 The STA382BW offers the possibility to share the filter coefficients between the two processing cha...

Page 27: ...be used to perform LFE This configuration and features ensure the backward compatibility with previous Sound Terminal products Figure 5 Processing path second part 2 1 output with individually configu...

Page 28: ...10 biquad filters are available for dedicated processing Please refer to Section 4 3 STCompressorTM for further information about this feature Figure 7 Processing path second part 2 1 output configur...

Page 29: ...ling block is running at 96 kHz It is not recommended to use the x3 oversampling feature when Fs 32 kHz because of the PLL maximum frequency constraint 4 3 STCompressorTM The STCompressorTM STC from n...

Page 30: ...ter 4 1 Processing data path please refer to the appropriate paragraphs and registers 4 3 2 Band splitter The band splitter block is used to divide the signal into 2 sub bands typically low and high f...

Page 31: ...eter The level meter block measures the input signal level in dB Two kinds of measures are performed peak and RMS The mapper configuration and the input signal automatically determine which measuremen...

Page 32: ...ld which represents the maximum output power allowed The signal is limited to avoid unpredictable effects and damages The compressor threshold the limiter threshold and the compressor rate are all use...

Page 33: ...ior as a limiter Table 10 Compressor ratio Compressor ratio Ratio value 0 1 1 1 1 1 25 2 1 1 5 3 1 1 75 4 1 2 5 1 2 5 6 1 3 7 1 3 5 8 1 4 9 1 4 5 10 1 5 11 1 5 5 12 1 6 13 1 7 14 1 8 15 1 16 INPUT L T...

Page 34: ...lowing equation The release rate is user selectable and its range is 0 0078 1 dB ms with a 0 0039 dB ms step 4 3 6 Dynamic attack Due to its dynamic the input signal may exceed the limiter threshold b...

Page 35: ...ullify the STC effect Each sub band has its own and independent offset Its range is 0 48 dB with a 0 25 dB step Table 12 Figure 12 Offset effect 4 3 8 Stereo link The stereo link feature allows applyi...

Page 36: ...effDecValue 0 where CoeffI2CValue is the final decimal value to be converted into hexadecimal notation while CoeffDecValue is the coefficient value in decimal notation to start from Output Ch 0 Attenu...

Page 37: ...xample Original value dec I2 C value hex 48 00 0x600000 24 00 0x300000 16 00 0x200000 12 00 0x180000 06 00 0x0C0000 02 00 0x040000 01 00 0x020000 01 00 0xFE0000 02 00 0xFC0000 06 00 0xF40000 12 00 0xE...

Page 38: ...16 0 25 dB ms 0x200000 0x5B LT limiter threshold 24 12 0 25 dB 0x000000 0x5C CR compressor ratio 0 15 1 index 0x000000 0x5D CT compressor threshold 48 0 0 25 dB 0x000000 CH1 Band 0 DRC 2 0x5E RR rele...

Page 39: ...0x45 B1 2 1 1 2 2 4 4 0x000000 0x46 B2 1 1 2 2 4 4 0x000000 0x47 A1 2 1 1 2 2 4 4 0x000000 0x48 A2 1 1 2 2 4 4 0x000000 0x49 B0 2 1 1 2 2 4 4 0x100000 Band 1 BQ0 0x4A B1 2 1 1 2 2 4 4 0x000000 0x4B B...

Page 40: ...signal SCL is stable in the high state A START condition must precede any command for data transfer 5 1 3 Stop condition STOP is identified by a low to high transition of the data bus SDA signal whil...

Page 41: ...erminates the transfer by generating a STOP condition 5 4 2 Current address multi byte read The multi byte read modes can start from any internal address Sequential data bytes are read from sequential...

Page 42: ...AD DEV ADDR ACK START RW SUB ADDR ACK DEV ADDR ACK STOP RANDOM ADDRESS READ DATA NO ACK W R T R A T S DEV ADDR ACK START DATA ACK DATA ACK STOP SEQUENTIAL CURRENT READ DATA NO ACK DEV ADDR ACK START R...

Page 43: ...D3 D2 D1 D0 0x00 CLK CLK_CFG 3 0 I2S 0x01 STATUS FAULT DRCCRC EQCRC BADPWM I2SERR PLLUL 0x02 RESET SRESET 0x03 SVOL SVOL 1 0 0x04 MVOL MVOL 7 0 0x05 FINEVOL FINE 1 0 0x06 CH1VOL CH1VOL 7 0 0x07 CH2VO...

Page 44: ...C4B8 0x33 A2CF3 C4B7 C4B6 C4B5 C4B4 C4B3 C4B2 C4B1 C4B0 0x34 B0CF1 C5B23 C5B22 C5B21 C5B20 C5B19 C5B18 C5B17 C5B16 0x35 B0CF2 C5B15 C5B14 C5B13 C5B12 C5B11 C5B10 C5B9 C5B8 0x36 B0CF3 C5B7 C5B6 C5B5 C5...

Page 45: ...0x6A F3XCFG2 F3X_FAULT F3X_SM_SLOPE 2 0 F3X_MUTE F3X_ENA 0x6B STCCFG0 NP_ CRCRES 0x6C STCCFG1 STC_LNK 0x6F MTH0 MTH 7 0 0x70 CHPSINC CHPI INITCNT 3 0 CHPRD 0x71 BQCHKE0 BQ_CKE 7 0 0x72 BQCHKE1 BQ_CKE...

Page 46: ...depends on CONFB register status D7 D6 D5 D4 D3 D2 D1 D0 FAULT DRCCRC EQCRC BADPWM Reserved Reserved I2SERR PLLUL NA NA NA NA NA NA NA NA Table 16 STATUS register Bit R W RST Name Description 7 R FAU...

Page 47: ...48 kHz 96 kHz or 192 kHz D7 D6 D5 D4 D3 D2 D1 D0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved SRESET 0 0 0 0 0 0 0 0 Table 17 RESET register Bit R W RST Name Description 0 R W 0 SRE...

Page 48: ...witchoff 0x01 Mute 0x02 Mute PWM on 0x03 Mute PWM on others volume MVOL 255 2 dB 1 1 If the volume is below 60 dB the level will be approximated to 1 dB step 6 R W 0 5 R W 0 4 R W 0 3 R W 0 2 R W 0 1...

Page 49: ...L 159 2 dB 1 1 If the volume is below 60 dB the level will be approximated to 1 dB step 6 R W 0 5 R W 0 4 R W 1 3 R W 1 2 R W 1 1 R W 1 0 R W 1 D7 D6 D5 D4 D3 D2 D1 D0 CH2VOL 7 0 1 0 0 1 1 1 1 1 Table...

Page 50: ...ER configuration selection OPER 1 0 Output configuration PBTL enable 00 2 channel full bridge power 2 channel data out 1A 1B 1A 1B 2A 2B 2A 2B LineOut1 3A 3B LineOut2 4A 4B Line out configuration dete...

Page 51: ...nel 1 LPF LineOut1 OUT3B LPF LineOut2 OUT4B OUT4A OUT3A Half Bridge Half Bridge Half Bridge Half Bridge OUT1A OUT1B OUT2A OUT2B Channel 3 Channel 1 Channel 2 Half Bridge Half Bridge Half Bridge Half B...

Page 52: ...FX1 B FFX2 A FFX 2B OUT1A OUT1B OUT2A OUT2B Power Bridge OUT1A OUT1B OUT2A OUT2B FFX3 A FFX3B FFX4 A FFX 4B OUT3A OUT3B OUT4A OUT4B FFX modulator REMAP FFX1A FFX1 B FFX2 A FFX 2B OUT1A OUT1B OUT2A OUT...

Page 53: ...gured as line out ternary FFX4A 4B configured as line out ternary On channel 3 line out LOC bits 00 reg 0x17 bit D7 D6 the same data as channel 1 processing is sent On channel 4 line out LOC bits 00 t...

Page 54: ...ion channel 3 has full control volume EQ etc On OUT3 OUT4 channels channel 1 and channel 2 PWM are replicated In this configuration the PWM slot phase is the following as shown in Figure 22 Figure 22...

Page 55: ...ry FFX3A 3B configured as ternary FFX4A 4B is not used In this configuration channel 3 has full control volume EQ etc On OUT4 channel the external bridge control signals are muxed In this configuratio...

Page 56: ...APEQ PEQ Reserved AMDRC MDRCE DRC 0 0 1 0 0 0 0 0 Table 25 FUNCT register Bit R W RST Name Description 6 R W 0 CRC 0 disable CRC computation and comparison 1 enable CRC computation and comparison 5 R...

Page 57: ...31 For the user programmable mode use the formulas below to compute the high pass filters where alpha 1 sin 0 cos 0 and 0 is the cutoff frequency A first order filter is recommended to guarantee that...

Page 58: ...is determined by both the MCSx and the IR input rate register bits The MCSx bits determine the PLL factor generating the internal clock and the IR bit determines the oversampling ratio used internall...

Page 59: ...48 00 64 fs NA 576 fs 128 fs 256 fs 384 fs 512 fs 768 fs 88 2 96 01 64 fs 32 fs NA 64 fs 128 fs 192 fs 256 fs 384 fs 176 4 192 1X 64 fs 32 fs NA 32 fs 64 fs 96 fs 128 fs 192 fs Table 29 Internal inter...

Page 60: ...as the fault indication exists This feature is enabled by default but can be bypassed by setting the FDRB control bit to 1 6 14 Configuration register B addr 0x12 6 14 1 Serial data interface The STA...

Page 61: ...Left right justified 16 bit data 48 fs 0000 0 I2 S 16 to 23 bit data 0001 0 Left justified 16 to 24 bit data 0010 0 Right justified 24 bit data 0110 0 Right justified 20 bit data 1010 0 Right justifie...

Page 62: ...it data 1110 1 Left right justified 16 bit data 48 fs 0100 1 I2 S 23 bit data 0100 1 I2 S 20 bit data 1000 1 I2 S 18 bit data 1100 1 LSB first I2 S 16 bit data 0001 1 Left justified 24 bit data 0101 1...

Page 63: ...e default settings of these registers map each I2S input channel to its corresponding processing channel 6 15 Configuration register C addr 0x13 6 15 1 FFX compensating pulse size register Table 35 De...

Page 64: ...re any EQ updates only have to be performed once Table 38 Compensating pulse size CSZ 3 0 Compensating pulse size 0000 0 ns 0 ticks compensating pulse size 0001 20 ns 1 tick clock period compensating...

Page 65: ...ced to approximately 83 dB in this mode which is still greater than the SNR of AM radio Table 42 Zero detect mute enable Bit R W RST Name Description 6 R W 0 ZDE Setting of 1 enables the automatic zer...

Page 66: ...output 50 duty cycle Table 46 PWM speed mode Bit R W RST Name Description 4 R W 0 PWMS 0 Normal speed 384 kHz all channels 1 Odd speed 341 3 kHz all channels Not suitable for binary BTL mode Table 47...

Page 67: ...ter state is preserved once the device recovers from power down 6 18 6 External amplifier power down The EAPD register directly disables enables the internal power circuitry When EAPD 0 the internal p...

Page 68: ...output configuration 00 Line output fixed no volume no EQ 01 Line output variable CH3 volume effects line output no EQ 10 Line output variable with EQ CH3 volume effects line output 11 Reserved Bit R...

Page 69: ...e approximately 96 kHz A hard instantaneous mute can be obtained by programming a value of 0xFF 255 to any channel volume register or the master volume register When volume offsets are provided via th...

Page 70: ...quency selection AMAM 2 0 48 kHz 96 kHz input fs 44 1 kHz 88 2 kHz input fs 000 0 535 MHz 0 720 MHz 0 535 MHz 0 670 MHz 001 0 721 MHz 0 900 MHz 0 671 MHz 0 800 MHz 010 0 901 MHz 1 100 MHz 0 801 MHz 1...

Page 71: ...z 0100 140 Hz 0101 160 Hz 0110 180 Hz 0111 200 Hz 1000 220 Hz 1001 240 Hz 1010 260 Hz 1011 280 Hz 1100 300 Hz 1101 320 Hz 1110 340 Hz 1111 360 Hz D7 D6 D5 D4 D3 D2 D1 D0 Reserved Reserved Reserved Res...

Page 72: ...be set to output a binary PWM stream In this mode output A of a channel is considered the positive output and output B is the negative inverse 6 21 5 Limiter select Limiter selection can be made on a...

Page 73: ...6 22 Tone control register addr 0x22 6 22 1 Tone control Table 66 Channel output mapping as a function of C3OM bits C3OM 1 0 Channel x output source from 00 Channel1 01 Channel 2 10 Channel 3 D7 D6 D5...

Page 74: ...annels in unison The limiter attack thresholds are determined by the LxAT registers if the EATHx 7 bit D7 of register 0x43 or 0x45 bits are set to 0 else the thresholds are determined by EATHx 6 0 It...

Page 75: ...n the release rate register The gain can never be increased past its set value and therefore the release only occurs if the limiter has already reduced the gain The release threshold value can be used...

Page 76: ...t Slow 0000 0 5116 Fast Slow 0001 2 7072 0001 0 1370 0010 2 2560 0010 0 0744 0011 1 8048 0011 0 0499 0100 1 3536 0100 0 0360 0101 0 9024 0101 0 0299 0110 0 4512 0110 0 0264 0111 0 2256 0111 0 0208 100...

Page 77: ...on of LxRT bits AC mode LxAT 3 0 AC dB relative to fs LxRT 3 0 AC dB relative to fs 0000 12 0000 0001 10 0001 29 dB 0010 8 0010 20 dB 0011 6 0011 16 dB 0100 4 0100 14 dB 0101 2 0101 12 dB 0110 0 0110...

Page 78: ...old as a function of LxAT bits DRC mode Table 73 Limiter release threshold as a function of LxRT bits DRC mode LxAT 3 0 DRC dB relative to volume LxRT 3 0 DRC dB relative to volume LxAT 0000 31 0000 0...

Page 79: ...ters addr 0x27 0x37 6 24 1 Coefficient address register 6 24 2 Coefficient b1 data register bits 23 16 6 24 3 Coefficient b1 data register bits 15 8 6 24 4 Coefficient b1 data register bits 7 0 D7 D6...

Page 80: ...0 C2B23 C2B22 C2B21 C2B20 C2B19 C2B18 C2B17 C2B16 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 C2B15 C2B14 C2B13 C2B12 C2B11 C2B10 C2B9 C2B8 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 C2B7 C2B6 C2B5 C2B4 C2B3...

Page 81: ...coefficient base address five sets of three store the values of the 24 bit coefficients to be written or that were read and one contains bits used to control the write read of the coefficient s to fro...

Page 82: ...n I2C address 0x2C 8 Read the bottom 8 bits of coefficient b2 in I2C address 0x2D 9 Read the top 8 bits of coefficient a1 in I2C address 0x2E 10 Read the middle 8 bits of coefficient a1 in I2C address...

Page 83: ...Write the top 8 bits of coefficient a2 in I2C address 0x31 12 Write the middle 8 bits of coefficient a2 in I2C address 0x32 13 Write the bottom 8 bits of coefficient a2 in I2C address 0x33 14 Write th...

Page 84: ...iquads use by default the extended coefficient range 4 4 Xover filters use only the standard coefficients range 1 1 By default all user defined filters are pass through where all coefficients are set...

Page 85: ...0x28 Channel 1 2 Biquad 5 for XO 000 High pass 2nd order filter for XO 000 C12H0 b1 2 0x000000 41 0x29 C12H1 b2 0x000000 42 0x2A C12H2 a1 2 0x000000 43 0x2B C12H3 a2 0x000000 44 0x2C C12H4 b0 2 0x4000...

Page 86: ...tenuation by default When PS48DB is set to 1 a 48 dB offset is applied to the coefficient RAM value so post scale can act as a gain too 6 26 2 Extended attack rate The attack rate shown in Table 68 ca...

Page 87: ...red as user programmable the corresponding coefficients are stored respectively in addresses 0x20 0x24 BQ5 0x25 0x29 BQ6 0x2A 0x2E BQ7 as given in Table 74 Note The BQx bits are ignored if BQL 0 or if...

Page 88: ...uency from the pad D7 D6 D5 D4 D3 D2 D1 D0 PLL_FRAC 15 8 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 PLL_FRAC 7 0 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 PLL_DITH 1 0 PLL_NDIV 5 0 0 0 0 0 0 0 0 0 D7 D6 D5...

Page 89: ...integer ratio 1 PLL use fractional ratio 5 R W 0 PLL_STB PLL synchronous divider changes strobe 4 R W 0 PLL_STBBYP 0 PLL_STB is active 1 PLL_STB control is bypassed 3 R W 0 PLL_IDIV 3 0 Input PLL div...

Page 90: ...means that OUTxx is shorted to Vcc finally OUTSH 0 means that OUT1B is shorted to OUT2A To be noted that once the check is performed and the tristate released the short protection is not active anymo...

Page 91: ...ated by dotted lines in the figure If one of the three tests or all fail the power bridge outputs are kept in the tristate until the procedure is restarted with a new EAPD toggling In this figure EAPD...

Page 92: ...PWDN function is enabled and after 13 million clock cycles PLL internal frequency the bridge is put in power down tristate mode There is also the possibility to change this behavior so that the power...

Page 93: ...2 and in case of power down assertion pin 42 is tied to LPDP The LPDP bit when set negates the value programmed as the LPD value refer to the following table Table 87 External amplifier enabler config...

Page 94: ...omputed as TH BPTH 2 1 128 100 If the measured PWM duty cycle is detected greater than or equal to TH for more than BPTIM PWM periods the corresponding PWM bit will be set in register 0x01 In case of...

Page 95: ...t level is detected greater than threshold hysteresis The measured level is then reported for each input channel on registers ZCCCFG1 ZCCCFG2 ZCCCFG3 ZCCCFG4 according to the following equation Value_...

Page 96: ...hat any write operation to the MTH bits will set the low threshold If the zero mute block does not detect mute it will mute the output when the current RMS value falls below the low threshold If the z...

Page 97: ...selects the gain of the F3X analog out path 0 HP out When the MVOL Channel Vol is 0 dBFs a 0 dBFs input will generate a 40 mW output on a 32 ohm load 3 3V supply 1 Line out When the MVOL Channel Vol i...

Page 98: ...X_ENA 1 1 1 0 1 1 1 0 Table 93 F3X configuration register 1 Bit R W RST Name Description 7 R W 0 F3XLNK 0 F3X normal control mode 1 F3X mute unmute linked to HP Line mute Table 94 F3X configuration re...

Page 99: ...CRC comparison error D7 D6 D5 D4 D3 D2 D1 D0 Reserved Reserved Reserved Reserved Reserved Reserved STC_LNK Reserved 0 0 0 0 0 0 0 0 Table 98 STCCFG1 register Bit R W RST Name Description 1 R W 0 STC_...

Page 100: ...2 XCCKE 1 XCCKE 0 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 XCCKE 15 XCCKE 14 XCCKE 13 XCCKE 12 XCCKE 11 XCCKE 10 XCCKE 9 XCCKE 8 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 XCCKE 23 XCCKE 22 XCCKE 21 XCCKE...

Page 101: ...O bit is not set In case of checksum errors i e the internally computed didn t match the reference an automatic device reset action can be activated This function is enabled when the BCAUTO or XCAUTO...

Page 102: ...tch has occurred and therefore that the device went through a reset cycle The previous example is intended for biquad CRC bank calculation but it can be easily extended to MDRC XOver CRC computation 6...

Page 103: ...Coefficients direct access multiple write operation Direct single read procedure 1 Set reg 0x7E bit 0 to 1 and bit 1 to 0 to enable the direct RAM access in single read mode 2 Read the coefficient val...

Page 104: ...AUTO XO3 XO2 XO1 XO0 AMAM2 AMAM1 AMAM0 AMAME 0E C1CFG C1OM1 C1OM0 C1LS1 C1LS0 C1BO C1VBP C1EQBP C1TCB 0F C2CFG C2OM1 C2OM0 C2LS1 C2LS0 C2BO C2VBP C2EQBP C2TCB 10 C3CFG C3OM1 C3OM0 C3LS1 C3LS0 C3BO C3...

Page 105: ...16 2F MTH1 MTH 15 8 31 EQCFG XOB 32 EATH1 EATHEN1 EATH1 6 0 33 ERTH1 ERTHEN1 ERTH1 6 0 34 EATH2 EATHEN2 EATH2 6 0 35 ERTH2 ERTHEN2 ERTH2 6 0 36 CONFX MDRCE PS48DB XAR1 XAR2 BQ5 BQ6 BQ7 37 SVUP SVUP_...

Page 106: ...X_ FAULT F3X_SM_SLOPE 2 0 F3X_ MUTE F3X_ENA 5A STCCFG0 LIM_BYP STC_BYP STC_ENA NP_ CRCRES NP_CRC_ GO 5B STCCFG1 STC_LNK BRC_EN 5E MTH0 MTH 7 0 5F CHPSINC CHPI INITCNT 3 0 CHPRD 60 BQCHKE0 BQ_CKE 7 0 6...

Page 107: ...e register bits The MCSx bits determine the PLL factor generating the internal clock and the IR bit determines the oversampling ratio used internally In Table 103 MCS 111 and 110 indicate that BICKI h...

Page 108: ...0 which directs the power output block to begin recovery holds it at 0 for period of time in the range of 0 1 ms to 1 second as defined by the fault detect recovery constant register FDRC registers 0x...

Page 109: ...al clock BICKI and serial data 1 and 2 SDI12 The SAI bits D3 to D0 and the SAIFB bit D4 are used to specify the serial data format The default serial data format is I2S MSB first Available formats are...

Page 110: ...s 0000 0 I2 S 16 to 23 bit data 0001 0 Left justified 16 to 24 bit data 0010 0 Right justified 24 bit data 0110 0 Right justified 20 bit data 1010 0 Right justified 18 bit data 1110 0 Right justified...

Page 111: ...erial audio input formats for LSB first SAIFB 1 BICKI SAI 3 0 SAIFB Interface format 32 fs 1100 1 I2 S 15 bit data 1110 1 Left right justified 16 bit data 48 fs 0100 1 I2 S 23 bit data 0100 1 I2 S 20...

Page 112: ...an be mapped to any internal processing channel via the channel input mapping registers This allows for flexibility in processing The default settings of these registers map each I2S input channel to...

Page 113: ...scription 2 R W 1 CSZ0 When OM 1 0 11 this register determines the size of the FFX compensating pulse from 0 clock ticks to 15 clock periods 3 R W 1 CSZ1 4 R W 1 CSZ2 5 R W 0 CSZ3 Table 114 Compensati...

Page 114: ...urement address 0x50 0x54 0x2E 0x2F and 0x5E 7 4 5 Submix mode enable 7 5 Configuration register E addr 0x04 Table 116 Post scale link Bit R W RST Name Description 3 R W 1 PSL 0 Each channel uses indi...

Page 115: ...ks are audible 7 5 5 Soft volume update enable Table 120 Noise shaper bandwidth selection Bit R W RST Name Description 2 R W 0 NSBW 1 Third order NS 0 Fourth order NS Table 121 AM mode enable Bit R W...

Page 116: ...0 Selects the output configuration 1 R W 0 OCFG1 Table 126 Output configuration engine selection OCFG 1 0 Output configuration PBTL enable 00 2 channel full bridge power 2 channel data out 1A 1B 1A 1B...

Page 117: ...nnel 2 Channel 1 LPF LineOut1 OUT3B LPF LineOut2 OUT4B OUT4A OUT3A Half Bridge Half Bridge Half Bridge Half Bridge OUT1A OUT1B OUT2A OUT2B Channel 3 Channel 1 Channel 2 Half Bridge Half Bridge Half Br...

Page 118: ...MAP FFX1A FFX1 B FFX2 A FFX 2B OUT1A OUT1B OUT2A OUT2B Power Bridge OUT1A OUT1B OUT2A OUT2B FFX3 A FFX3B FFX4 A FFX 4B OUT3A OUT3B OUT4A OUT4B FFX modulator REMAP FFX1A FFX1 B FFX2 A FFX 2B OUT1A OUT1...

Page 119: ...rnary FFX3A 3B configured as C3B0 default ternary line out FFX4A 4B configured as C4B0 default ternary line out On channel 3 line out LOC bits 00 the same data as channel 1 processing is sent On chann...

Page 120: ...configuration channel 3 has full control volume EQ etc On OUT3 OUT4 channels channel 1 and channel 2 PWM are replicated In this configuration the PWM slot phase is the following as shown in Figure 37...

Page 121: ...2B0 default ternary FFX3A 3B configured as C3B0 default ternary FFX4A 4B is not used In this configuration channel 3 has full control volume EQ etc On OUT4 channel the external bridge control signals...

Page 122: ...output begins a soft mute After the mute condition is reached EAPD is asserted to power down the power stage then the master clock to all internal hardware except the I2 C block is gated This places t...

Page 123: ...iguration The source of the line output is always channel 1 and 2 inputs Table 132 External amplifier power down Bit R W RST Name Description 7 R W 0 EAPD 0 External power stage power down active 1 No...

Page 124: ...RST Name Description 3 R W 0 C3M Channel 3 mute 0 No mute condition It is possible to set the channel volume 1 Channel 3 in hardware mute 2 R W 0 C2M Channel 2 mute 0 No mute condition It is possible...

Page 125: ...r any channel whose total volume is less than 80 dB is muted All changes in volume take place at zero crossings when ZCE 1 Configuration register E addr 0x04 on a per channel basis as this creates the...

Page 126: ...8 Audio preset AM switching frequency selection AMAM 2 0 48 kHz 96 kHz input fs 44 1 kHz 88 2 kHz input fs 000 0 535 MHz 0 720 MHz 0 535 MHz 0 670 MHz 001 0 721 MHz 0 900 MHz 0 671 MHz 0 800 MHz 010 0...

Page 127: ...00 140 Hz 0101 160 Hz 0110 180 Hz 0111 200 Hz 1000 220 Hz 1001 240 Hz 1010 260 Hz 1011 280 Hz 1100 300 Hz 1101 320 Hz 1110 340 Hz 1111 360 Hz D7 D6 D5 D4 D3 D2 D1 D0 C1OM1 C1OM0 C1LS1 C1LS0 C1BO C1VPB...

Page 128: ...isters Each individual channel output can be set to output a binary PWM stream In this mode output A of a channel is considered the positive output and output B is the negative inverse 7 9 5 Limiter s...

Page 129: ...outputs 7 10 Tone control register addr 0x11 7 10 1 Tone control Table 146 Channel output mapping as a function of CxOM bits CxOM 1 0 Channel x output source from 00 Channel1 01 Channel 2 10 Channel...

Page 130: ...f needed adjusts the gain of the mapped channels in unison The limiter attack thresholds are determined by the LxAT registers if the EATHx 7 bits are set to 0 else the thresholds are determined by EAT...

Page 131: ...dent upon the release rate register The gain can never be increased past its set value and therefore the release only occurs if the limiter has already reduced the gain The release threshold value can...

Page 132: ...0 3 1584 Fast Slow 0000 0 5116 Fast Slow 0001 2 7072 0001 0 1370 0010 2 2560 0010 0 0744 0011 1 8048 0011 0 0499 0100 1 3536 0100 0 0360 0101 0 9024 0101 0 0299 0110 0 4512 0110 0 0264 0111 0 2256 011...

Page 133: ...as a function of LxRT bits AC mode LxAT 3 0 AC dB relative to fs LxRT 3 0 AC dB relative to fs 0000 12 0000 0001 10 0001 29 dB 0010 8 0010 20 dB 0011 6 0011 16 dB 0100 4 0100 14 dB 0101 2 0101 12 dB...

Page 134: ...tack threshold as a function of LxAT bits DRC mode Table 153 Limiter release threshold as a function of LxRT bits DRC mode LxAT 3 0 DRC dB relative to volume LxRT 3 0 DRC db relative to volume LxAT 00...

Page 135: ...ntrol registers addr 0x16 0x26 7 12 1 Coefficient address register 7 12 2 Coefficient b1 data register bits 23 16 7 12 3 Coefficient b1 data register bits 15 8 7 12 4 Coefficient b1 data register bits...

Page 136: ...D3 D2 D1 D0 C2B23 C2B22 C2B21 C2B20 C2B19 C2B18 C2B17 C2B16 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 C2B15 C2B14 C2B13 C2B12 C2B11 C2B10 C2B9 C2B8 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 C2B7 C2B6 C2B...

Page 137: ...is function One contains a coefficient base address five sets of three store the values of the 24 bit coefficients to be written or that were read and one contains bits used to control the write read...

Page 138: ...icient b2 in I2C address 0x1B 8 Read the bottom 8 bits of coefficient b2 in I2C address 0x1C 9 Read the top 8 bits of coefficient a1 in I2C address 0x1D 10 Read the middle 8 bits of coefficient a1 in...

Page 139: ...ddress 0x1F 11 Write the top 8 bits of coefficient a2 in I2C address 0x20 12 Write the middle 8 bits of coefficient a2 in I2C address 0x21 13 Write the bottom 8 bits of coefficient a2 in I2C address 0...

Page 140: ...oefficient range 4 4 Xover filters use only the standard coefficients range 1 1 By default all user defined filters are pass through where all coefficients are set to 0 except the channel 1 and 2 b0 2...

Page 141: ...00 High pass 1st order filter for XO 000 C12H0 b1 2 0x000000 41 0x29 C12H1 b2 0x000000 42 0x2A C12H2 a1 2 0x000000 43 0x2B C12H3 a2 0x000000 44 0x2C C12H4 b0 2 0x400000 45 0x2D Channel 3 Biquad for XO...

Page 142: ...ocked 7 15 EQ coefficients configuration register addr 0x31 The XOB bit can be used to bypass the crossover filters Logic 1 means that the function is not active In this case the high pass crossover f...

Page 143: ...high frequency components while limiter 2 DRC2 is used to control the low frequency components see Chapter 7 11 The cutoff frequency of the high pass filters can be user defined XO 3 0 0 or selected f...

Page 144: ...mbination For second order filters it is not possible to give a closed formula to get the best coefficients but empirical adjustment should be done DRC settings The DRC blocks used by B2 DRC are the s...

Page 145: ...biquad 7 When filters from the 5th to 7th are configured as user programmable the corresponding coefficients are stored respectively in addresses 0x20 0x24 BQ5 0x25 0x29 BQ6 0x2A 0x2E BQ7 as given in...

Page 146: ...the SVUP 4 0 value Table 163 Soft volume update enable decrease When SVDWE 1 the volume down rate is defined by the SVDW 4 0 bits according to the following formula volume down rate 48 N 1 dB ms where...

Page 147: ...e will be defined only by the CxVol registers Fine tuning steps can be set according to the following table for channels 1 2 3 and master volume Table 164 Volume fine tuning steps D7 D6 D5 D4 D3 D2 D1...

Page 148: ...plications and to provide flexibility to the user a manual PLL configuration can be used setting PLL_DIRP to 1 VRESEN VRESTG Mode 0 0 Extra volume resolution disabled 0 1 Extra volume resolution disab...

Page 149: ...ing enabled rectangular 11 Reserved 6 R W 0 5 R W 0 NDIV PLL loop divider 4 R W 0 3 R W 0 2 R W 0 1 R W 0 0 R W 0 Table 168 PLL register 0x44 bits Bit R W RST Name Description 7 R W 0 PLL_DPD 0 any PL...

Page 150: ...n VCCSH means that OUTxx is shorted to Vcc finally OUTSH 0 means that OUT1B is shorted to OUT2A Table 169 PLL register 0x45 bits Bit R W RST Name Description 5 R W 0 PLL_DIRP 0 PLL configuration is de...

Page 151: ...ts to indicate that the bits are carrying the status of the previous EAPD 0 1 toggling to be noted that after reset this state is meaningless since no EAPD transition occurs GND related SHOK bits are...

Page 152: ...channel 2 Crossover biquad does not have the availability of this feature maintaining the 1 1 range unchanged 7 22 Miscellaneous registers address 0x4B 0x4C 7 22 1 Rate power down enable RPDNEN bit ad...

Page 153: ...on and not for a power down applied through the IIC interface Refer to Section 7 22 5 if programming a different number of clock cycles is needed 7 22 3 Channel PWM enable CPWMEN bit address 0x4B bit...

Page 154: ...ing table Table 173 PNDLSL bits configuration 7 22 6 Short circuit check enable bit address 0x4C bit D0 This bit when enabled will activate the short circuit checks before any power bridge activation...

Page 155: ...BPTH 2 1 128 100 If the measured PWM duty cycle is detected greater than or equal to TH for more than BPTIM PWM periods the corresponding PWM bit will be set in register 0x4E In case of binary modulat...

Page 156: ...me less than threshold hysteresis Once muted the PWM will be unmuted when the input level is detected greater than threshold hysteresis The measured level is then reported for each input channel on re...

Page 157: ...re the low threshold the WTHH bit must be set to 1 so that any write operation to the MTH bits will set the low threshold If the zero mute block does not detect mute it will mute the output when the c...

Page 158: ...Name Description 7 R W 0 HPLN When F3X is connected to the internal HP Line driver this bit selects the gain of the F3X analog out path 0 HP out When the MVOL Channel Vol is 0 dBFs a 0 dBFs input will...

Page 159: ...MUTE F3X_ENA NA 1 1 0 1 1 1 0 Table 178 F3X configuration register 1 Bit R W RST Name Description 7 R W 0 F3XLNK 0 F3X normal control mode 1 F3X mute unmute linked to HP Line mute Table 179 F3X config...

Page 160: ...ssed 5 R W 1 STC_BYP 0 STCompressorTM processing activated 1 STCompressorTM is in pass through 4 R W 1 STC_EN 0 STCompressorTM is switched off no configuration is possible in this state 1 STCompressor...

Page 161: ...M waveform This functionality cannot be activated when the PWMS bit address 0x15 bit D4 is set to 1 D7 D6 D5 D4 D3 D2 D1 D0 Reserved Reserved CHPI INITCNT 3 0 CHPRD 0 0 0 1 1 0 0 1 Bit R W RST Name De...

Page 162: ...4 D3 D2 D1 D0 XCCKE 23 XCCKE 22 XCCKE 21 XCCKE 20 XCCKE 19 XCCKE 18 XCCKE 17 XCCKE 16 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 BQCKR 7 BQCKR 6 BQCKR 5 BQCKR 4 BQCKR 3 BQCKR 2 BQCKR 1 BQCKR 0 0 0 0 0 0...

Page 163: ...the automatic reset activation is the following Download the set of coefficients RAM locations 0x00 0x27 Download the externally computed biquad checksum into registers BQCHKR Enable the checksum of...

Page 164: ...are reset 7 31 MISC4 address 0x7E D7 D6 D5 D4 D3 D2 D1 D0 reserved reserved reserved reserved reserved SRESET reserved reserved 0 0 0 0 0 0 0 0 Table 183 Misc register 3 Bit R W RST Name Description 2...

Page 165: ...interface on both the power output and on the line headphone out Figure 45 Regardless of the LINEINx pins input the F3Xx outputs can be connected to an external amplifier as an auxiliary analog outpu...

Page 166: ...1 Figure 45 F3X from SAI source to line headphone out application scheme Note For further information please refer to application note AN3959 2 0 channel demonstration board based on the STA382BW and...

Page 167: ...ation note AN3959 2 0 channel demonstration board based on the STA381BW and STA382BW 8 2 Headphone and 2 Vrms line out Figure 47 Headphone and line out block diagram Note For further information pleas...

Page 168: ...the line out headphone output Note The charge pump of the headphone and line out cannot drive a purely capacitive load Please refer to AN3959 2 0 channel demonstration board based on the STA381BW and...

Page 169: ...offers these devices in different grades of ECOPACK packages depending on their level of environmental compliance ECOPACK specifications grade definitions and product status are available at www st co...

Page 170: ...age dimensions Reference mm Min Typ Max A 0 80 0 90 1 00 A1 0 0 05 D 6 90 7 00 7 10 D2 5 65 5 70 5 75 E 6 90 7 00 7 10 E2 5 65 5 70 5 75 b 0 25 0 30 0 35 b1 0 20 0 25 0 30 e pad pitch 0 50 L1 0 05 0 1...

Page 171: ...STA382BW Revision history Doc ID 022783 Rev 1 171 172 10 Revision history Table 186 Document revision history Date Revision Changes 04 Apr 2012 1 Initial release Obsolete Product s Obsolete Product s...

Page 172: ...ANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS EXPRESSLY APPRO...

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Summary of Contents for Sound Termina STA382BWTR

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Summary of Contents for Sound Termina STA382BWTR

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