Register description: Sound Terminal compatibility
STA382BW
112/172
Doc ID 022783 Rev 1
happens. At the same time any processing related to the I
2
C configuration should be issued
only after the serial audio interface and the internal PLL are synchronous again.
Note:
Any mute or volume change causes some delay in the completion of the I
2
C operation due
to the soft volume feature. The soft volume phase change must be finished before any clock
desynchronization.
7.2.4
Delay serial clock enable
7.2.5
Channel input mapping
Each channel received via I
2
S can be mapped to any internal processing channel via the
channel input mapping registers. This allows for flexibility in processing. The default settings
of these registers map each I
2
S input channel to its corresponding processing channel.
Table 111.
Delay serial clock enable
Bit
R/W
RST
Name
Description
5
R/W
0
DSCKE
0: No serial clock delay
1: Serial clock delay by 1 core clock cycle to tolerate
anomalies in some I
2
S master devices
Table 112.
Channel input mapping
Bit
R/W
RST
Name
Description
6
R/W
0
C1IM
0: Processing channel 1 receives left I
2
S input
1: Processing channel 1 receives right I
2
S input
7
R/W
1
C2IM
0: Processing channel 2 receives left I
2
S input
1: Processing channel 2 receives right I
2
S input
Obsolete Product(s) - Obsolete Product(s)