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ST Sitronix ST7038 Manual Download Page 15

ST7038 

Ver 1.1 

15/61 

2007/01/25 

 

Figure 1 

The 4-Line SPI Mode access timing 

 

Figure 2 

The 3-Line SPI Mode access timing 

 

 

I

2

C Interface (PS[2:0] = "1, 0, 0") 

The I

2

C Interface uses two-signal to communicate between different ICs or modules. The two signals are SDA (Serial Data) 

and SCL (Serial Clock). Both lines must be connected to a pull-up resistor to provide the 

“

H

”

 voltage level. Data transfer may 

be initiated only when the bus is not busy. 
 
ST7038i  support  I

2

C  interface  with  only  write  function. 

Status  read  or  data  read  is  impossible

  (except  reading  the 

Acknowledge signal). The related signals are listed below: 

Ø

 

SCL: serial clock input

 

Ø

 

SDA_IN: serial data input

 

Ø

 

SDA_OUT: acknowledge response output

 

Ø

 

SA1~SA0: select the slave address and the 

available slave addresses are: 

“

0111100

”

 to 

“

0111111

”

.

 

 

l

 

BIT TRANSFER   
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH 
period of the clock pulse because changes in the data line at this time will be interpreted as a control signal. Bit transfer 
is illustrated in Figure 3. 

l

 

START AND STOP CONDITIONS   
Both SDA and SCL lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition on SDA while SCL is HIGH 
is defined as the START condition (S). A LOW-to-HIGH transition of SDA while SCL is HIGH is defined as the STOP 
condition (P). The START and STOP conditions are illustrated in Figure 4. 

l

 

SYSTEM CONFIGURATION   
The system configuration of I

2

C interface is illustrated in Figure 5. The related glossaries are listed below:   

Ø

 

Transmitter: the device sends the data to the bus

 

Ø

 

Master: the device, which initiates a transfer, generates clock signals and terminates a transfer

 

Ø

 

Slave: the device addressed by a master

 

Ø

 

Multi-Master:  more  than  one  master  can  attempt  to  control  the  bus  at  the  same  time  without  corrupting  the 
message

 

Ø

 

Arbitration: a procedure to ensure that, if more than one master tries to control the bus simultaneously, only one 
is allowed to do so and the message is not corrupted

 

Ø

 

Synchronization: a procedure to synchronize the clock signals of two or more devices.

 

 

Summary of Contents for Sitronix ST7038

Page 1: ...direction selectable by instruction l Selectable CGRAM CGROM size l Package Type COG GENERAL DESCRIPTION ST7038 dot matrix liquid crystal display controller can display alphanumeric Japanese kana characters and symbols It can be configured to drive a dot matrix liquid crystal display under the control of a microprocessor with 4 8 bit 6800 series or 8080 series 3 4 line serial or fast I 2 C interfa...

Page 2: ... 2 61 2007 01 25 PAD ARRANGEMENT l Chip Size 5476 2um X 906 2 um l Bump Pitch I O PAD 73um COM SEG PAD 45um l Bump size PAD No 001 057 55um X 60um PAD No 058 175 30um X 80um l Bump Height 17um l Chip Thickness 480um ...

Page 3: ...1590 94 379 49 CAP2N 1663 94 379 50 CAP4P 1736 71 379 51 CAP4P 1809 94 379 52 VRS 1892 1 379 53 V0 1965 26 379 54 V1 2053 56 379 PAD No PIN Name X Y 55 V2 2126 56 379 56 V3 2199 56 379 57 V4 2272 56 379 58 COM 12 2611 93 369 59 COM 11 2566 93 369 60 COM 10 2521 93 369 61 COM 9 2476 93 369 62 COM 8 2431 93 369 63 COM 7 2386 93 369 64 COM 6 2341 93 369 65 COM 5 2296 93 369 66 NC 2251 93 369 67 COM 4...

Page 4: ...3 07 369 138 SEG 62 988 07 369 139 SEG 63 1033 07 369 140 SEG 64 1078 07 369 141 SEG 65 1123 07 369 142 SEG 66 1168 07 369 143 SEG 67 1213 07 369 144 SEG 68 1258 07 369 145 SEG 69 1303 07 369 146 SEG 70 1348 07 369 147 SEG 71 1393 07 369 148 SEG 72 1438 07 369 149 SEG 73 1483 07 369 150 SEG 74 1528 07 369 151 SEG 75 1573 07 369 152 SEG 76 1618 07 369 153 SEG 77 1663 07 369 154 SEG 78 1708 07 369 1...

Page 5: ... CAP2N 1663 94 379 50 CAP4P 1736 71 379 51 CAP4P 1809 94 379 52 VRS 1892 1 379 53 V0 1965 26 379 54 V1 2053 56 379 PAD No PIN Name X Y 55 V2 2126 56 379 56 V3 2199 56 379 57 V4 2272 56 379 58 COM 8 2611 93 369 59 COM 7 2566 93 369 60 COM 6 2521 93 369 61 COM 5 2476 93 369 62 COM 4 2431 93 369 63 COM 3 2386 93 369 64 COM 2 2341 93 369 65 COM 1 2296 93 369 66 COMI1 2251 93 369 67 SEG 1 2206 93 369 6...

Page 6: ... SEG 72 988 07 369 139 SEG 73 1033 07 369 140 SEG 74 1078 07 369 141 SEG 75 1123 07 369 142 SEG 76 1168 07 369 143 SEG 77 1213 07 369 144 SEG 78 1258 07 369 145 SEG 79 1303 07 369 146 SEG 80 1348 07 369 147 SEG 81 1393 07 369 148 SEG 82 1438 07 369 149 SEG 83 1483 07 369 150 SEG 84 1528 07 369 151 SEG 85 1573 07 369 152 SEG 86 1618 07 369 153 SEG 87 1663 07 369 154 SEG 88 1708 07 369 155 SEG 89 17...

Page 7: ...63 94 379 50 CAP4P 1736 71 379 51 CAP4P 1809 94 379 52 VRS 1892 1 379 53 V0 1965 26 379 54 V1 2053 56 379 PAD No PIN Name X Y 55 V2 2126 56 379 56 V3 2199 56 379 57 V4 2272 56 379 58 COM 8 2611 93 369 59 COM 7 2566 93 369 60 COM 6 2521 93 369 61 COM 5 2476 93 369 62 COM 4 2431 93 369 63 COM 3 2386 93 369 64 COM 2 2341 93 369 65 COM 1 2296 93 369 66 COMI1 2251 93 369 67 SEG 1 2206 93 369 68 SEG 2 2...

Page 8: ... 943 07 369 138 SEG 72 988 07 369 139 SEG 73 1033 07 369 140 SEG 74 1078 07 369 141 SEG 75 1123 07 369 142 SEG 76 1168 07 369 143 SEG 77 1213 07 369 144 SEG 78 1258 07 369 145 SEG 79 1303 07 369 146 SEG 80 1348 07 369 147 SEG 81 1393 07 369 148 SEG 82 1438 07 369 149 SEG 83 1483 07 369 150 SEG 84 1528 07 369 151 SEG 85 1573 07 369 152 SEG 86 1618 07 369 153 SEG 87 1663 07 369 154 SEG 88 1708 07 36...

Page 9: ... 49 CAP2N 1663 94 379 50 CAP4P 1736 71 379 51 CAP4P 1809 94 379 52 VRS 1892 1 379 53 V0 1965 26 379 54 V1 2053 56 379 PAD No PIN Name X Y 55 V2 2126 56 379 56 V3 2199 56 379 57 V4 2272 56 379 58 NC 2611 93 369 59 NC 2566 93 369 60 NC 2521 93 369 61 NC 2476 93 369 62 NC 2431 93 369 63 NC 2386 93 369 64 NC 2341 93 369 65 NC 2296 93 369 66 COMI1 2251 93 369 67 SEG 1 2206 93 369 68 SEG 2 2161 93 369 6...

Page 10: ... 138 SEG 72 988 07 369 139 SEG 73 1033 07 369 140 SEG 74 1078 07 369 141 SEG 75 1123 07 369 142 SEG 76 1168 07 369 143 SEG 77 1213 07 369 144 SEG 78 1258 07 369 145 SEG 79 1303 07 369 146 SEG 80 1348 07 369 147 SEG 81 1393 07 369 148 SEG 82 1438 07 369 149 SEG 83 1483 07 369 150 SEG 84 1528 07 369 151 SEG 85 1573 07 369 152 SEG 86 1618 07 369 153 SEG 87 1663 07 369 154 SEG 88 1708 07 369 155 SEG 8...

Page 11: ...iver LCD drive voltage follower Address counter AC Data register DR Busy flag MPU interface Input output buffer Character generator RAM CGRAM 64 bytes Character generator ROM CGROM 10240 bits Cursor and blink controller Parallel serial converter and attribute circuit RS E DB4 to DB7 DB0 to DB3 VDD OSC COM1 to COM16 or 24 SEG1 to SEG100 or 80 XRESET VSS Voltage booster circuit COMI CLS V0 V4 VOUT P...

Page 12: ...lel interface DB7 DB0 are 8 bit bi directional data bus and should be connected to 8 bit data bus of the microprocessor When the chip select is not active CSB H DB7 DB0 are high impedance For parallel 4 bit parallel interface DB7 DB4 are used for data transfer between MPU and ST7038 DB3 DB0 are not used and must be left OPEN or connected to VDD For serial interface 3 line and 4 line DB7 serial dat...

Page 13: ...r Power for analog circuit Connect to 1 8V 3 3V power source VSS Power Power Ground VRS Power Power Reserved to monitor the internal Voltage Regulator reference level Must be left open CLS I Option Select to use internal external oscillation system 0 External clock will be input through OSC pin 1 Using internal clock and the OSC pin must be fixed to VDD OSC I Oscillation External clock input pin I...

Page 14: ...MPU 8080 series MPU A0 E R W RD WR Description H H H L H Read display data H H L H L Write display data L H H L H Read status L H L H L Write register instruction Note By fixing the RD E pin to H in 6800 series interface the CSB pin can be used as the Enable signal In this way the data is latched at the rising edge of CSB and the access type is determined by the signals A0 and WR R W Serial Interf...

Page 15: ...se because changes in the data line at this time will be interpreted as a control signal Bit transfer is illustrated in Figure 3 l START AND STOP CONDITIONS Both SDA and SCL lines remain HIGH when the bus is not busy A HIGH to LOW transition on SDA while SCL is HIGH is defined as the START condition S A LOW to HIGH transition of SDA while SCL is HIGH is defined as the STOP condition P The START an...

Page 16: ...eiver which is addressed must generate an acknowledge bit after the reception of each byte A master receiver must also generate an acknowledge bit after the reception of each byte that has been clocked out of the slave transmitter The device that acknowledges must pull down the SDA line during the LOW period of the acknowledge clock so that the SDA is stable LOW during the HIGH period of the ackno...

Page 17: ...by the data pointer The data pointer is automatically updated and the data is directed to the intended ST7038i device If the A0 bit of the last control byte is set to logic 0 these command bytes will be decoded and the setting of the device will be changed according to the received commands Only the addressed slave makes the acknowledgement after each byte At the end of the transmission the I 2 C ...

Page 18: ...ont stored in the Character Generator ROM CGROM The Display Data RAM DDRAM capacity is 80 x 8 bits or 80 characters The unused area in Display Data RAM DDRAM can be used as general data RAM Please refer to the following sections for the relationships between DDRAM address and display position on the LCD module under different display operation Please note that In following demonstration the DDRAM ...

Page 19: ...s of the first line and the start address of the second line are not consecutive For example 20 characters by 2 lines are displayed with 100 segments the default relation between DDRAM Address and display position is illustrated on the top of Figure 12 When display shift operation is performed the relation is changed just as shown in Figure 12 Figure 11 2 Line Display Mode Figure 12 2 Line Display...

Page 20: ...ion is illustrated in Figure 13 For example 16 characters by 3 lines are displayed with 80 segments the default relation between DDRAM Address and display position is illustrated on the top of Figure 14 When display shift operation is performed the relation is changed just as shown in Figure 14 Figure 13 3 Line Display Mode Figure 14 3 Line Display Mode with 20 Character Display ...

Page 21: ... 16 patterns are multiplexed with the Character Generator RAM CGRAM By using instruction to set OPR2 OPR1 customer can use the patterns stored in CGRAM to replace these 16 default patterns The detailed setting is illustrated in Table 7 User defined character patterns are also supported by changing the content in mask programmed ROM Table 5 illustrated the relation between Character Codes and Chara...

Page 22: ...0 1 1 1 1 1 1 0 1 0 0 1 0 1 0 0 1 0 1 1 0 0 1 0 1 1 0 1 0 0 0 1 0 0 0 0 4 0 0 1 0 0 1 1 1 1 0 0 0 0 0 Table 6 Relationship among CGRAM Address Character Code DDRAM Data Character Pattern CGRAM Data Notes 1 Character code bits 2 to 0 are identical with CGRAM address bits 5 to 3 the red block and red arrow These 3 bits indicate there are maximum 8 character patterns can be generated by CGRAM 2 CGRAM...

Page 23: ...7038 Ver 1 1 23 61 2007 01 25 Replaced By CGRAM Pattern Replaced By CGRAM Pattern Replaced By CGRAM Pattern Replaced By CGRAM Pattern Table 7 Use OPR2 OPR1 to configure the mapping between CGRAM and CGROM ...

Page 24: ...N RAM Mapping when SHLS 0 ICON RAM bits ICON Address b7 b6 b5 b4 b3 b2 b1 b0 00H ICON80 ICON79 ICON78 ICON77 ICON76 01H ICON75 ICON74 ICON73 ICON72 ICON71 02H ICON70 ICON69 ICON68 ICON67 ICON66 03H ICON65 ICON64 ICON63 ICON62 ICON61 04H ICON60 ICON59 ICON58 ICON57 ICON56 05H ICON55 ICON54 ICON53 ICON52 ICON51 06H ICON50 ICON49 ICON48 ICON47 ICON46 07H ICON45 ICON44 ICON43 ICON42 ICON41 08H ICON40 ...

Page 25: ...12 COM 4 1 COMI1 COM 13 16 COM 17 24 2 1 0 COM 20 13 COM 21 24 COMI1 COM 12 9 COM 8 1 1 COM 5 12 COM 4 1 COMI1 COM 13 16 COM 17 24 3 0 0 24 1 NC COM 20 13 COM 21 24 COMI1 NC SEG 1 80 NC COM 12 9 COM 8 1 COMI2 Output Pin Function Note 1 SHLC 1 COM scan direction is normal SHLC 0 COM scan direction is reversed Pin definition of COM is changed when SHLC 0 2 ICON COM COMI1 COMI2 scan direction will ne...

Page 26: ... Cursor position on 93 us 85 us 70 us Function Set 0 0 0 0 1 DL X X IS1 IS0 DL Interface data is 8 4 bits IS 1 0 select instruction table 93 us 85 us 70 us Set DDRAM Address 0 0 1 AC6 AC5 AC4 AC3 AC2 AC1 AC0 Set DDRAM address into AC address counter 93 us 85 us 70 us Read Status 0 1 BF AC6 AC5 AC4 AC3 AC2 AC1 AC0 Before next access Check BF will know if the internal operation is finished or not Th...

Page 27: ... Fon Ion ICON display on off Bon Set booster circuit on off Ron Set regulator circuit on off Fon Set follower circuit on off 93 us 85 us 70 us V0 Control 2 0 0 0 1 1 1 VC3 VC2 VC1 VC0 Set V0 Low nibble 93 us 85 us 70 us Instruction table 2 IS 1 0 1 0 Set Display Mode 0 0 0 0 0 1 UD DH N2 N1 UD Double Height Position DHu or DHd DH Double Height N2 N1 Display line number 93 us 85 us 70 us Select CGR...

Page 28: ...lay After each data access the cursor and display will be moved or shifted according to I D bit and S bit l I D Increment decrement of DDRAM address cursor blink after each byte data access I D 1 cursor blink moves to right and DDRAM address is increased by 1 I D 0 cursor blink moves to left and DDRAM address is decreased by 1 CGRAM operation is the same as DDRAM CGRAM address is automatically adj...

Page 29: ... parallel 4 bit bus to communicate with MPU When using parallel 4 bit bus mode each instruction needs to be transfer twice including this instruction l IS 1 0 Selects instruction table When IS 1 0 0 0 Normal instruction is selected refer instruction table 0 When IS 1 0 0 1 Extension instruction is selected refer instruction table 1 When IS 1 0 1 0 Extension instruction is selected refer instructio...

Page 30: ...Address Set CGRAM Address Set ICON RAM Address RAM set instruction can also determine the AC direction to RAM After write operation the address is adjusted by 1 automatically increase or decrease is controlled by the setting of Entry Mode Read Data from DDRAM CGRAM or ICON RAM This operation reads binary 8 bit data from DDRAM CGRAM or ICON RAM The selection of RAM DDRAM CGRAM or ICON RAM is contro...

Page 31: ...n shift is performed simultaneously on each line in all kinds of display line mode Each line is shifted individually The content kept in AC is not changed when performing Screen Shift operation Set CGRAM Address This instruction sets CGRAM address into AC This instruction makes CGRAM data available for MPU access Instruction Table 1 IS 1 0 0 1 Follower Control BS 2 1 Bias level selection 0 0 Selec...

Page 32: ...or more detailed information VC6 VC5 VC4 VC3 VC2 VC1 VC0 V0 V 0 0 0 0 0 0 0 2 000 0 0 0 0 0 0 1 2 024 0 0 0 0 0 1 0 2 048 0 0 0 0 0 1 1 2 071 1 1 1 1 1 0 0 4 952 1 1 1 1 1 0 1 4 976 1 1 1 1 1 1 0 5 000 1 1 1 1 1 1 1 5 024 ICON Power Control Setting ION BON RON FON H ICON display ON Built in Booster ON Built in Regulator ON Built in Follower ON L ICON display OFF Built in Booster OFF Built in Regul...

Page 33: ...COM1 8 is normal COM9 24 is double height DH 1 N2 0 N1 1 UD 1 COM17 24 is normal COM1 16 is double height l DH Display double height font 5X16 dot matrix control bit Please refer to the following table for detailed setting and description DH UD N2 0 N1 0 1 Line N2 0 N1 1 2 Line N2 1 N1 X 3 Line L X Normal Display DDRAM 00H 4FH Normal Display DDRAM 00H 27H Normal Display DDDRAM 00H 0FH H H COM1 16 ...

Page 34: ...de 0 0 1 Line Display mode 0 1 2 Line Display mode 1 X 3 Line Display mode Table 10 N 2 1 vs Display Line Number l Complete Display Modes UD DH N2 N1 Display Mode Description Duty X 0 0 0 1 Line Display mode 1 8 1 X 1 0 0 1 Line Display mode double height 1 16 1 X 0 0 1 2 Line Display mode 1 16 1 1 1 0 1 2 Line Display mode double height UP 1 24 1 0 1 0 1 2 Line Display mode double height DOWN 1 2...

Page 35: ...80 segments l SHLC Pin definition is changed when SHLC 0 SHLC 1 COM1 24 Row address 0 23 Normal SHLC 0 COM1 24 Row address 23 0 Invert Pin definition of COM is changed when SHLC 0 Please refer to Table 9 for the detailed output map Set Frame Rate FR 2 0 Set Frame Rate according the table below FR2 FR1 FR0 Frame Rate Hz 0 0 0 65 35 15 0 0 1 68 03 15 0 1 0 70 92 10 Default 0 1 1 74 07 15 1 0 0 77 52...

Page 36: ...d I 2 C operation The following figures are referential circuits connected with different kinds of MPU The microprocessor interface pins CSB WR RD A0 and D7 D0 should not be left floating in any operation mode l Intel 8051 interface 4 Bit parallel 6800 series l Intel 8051 interface 4 Bit parallel 8080 series l Intel 8051 interface 8 Bit parallel 6800 series l Intel 8051 interface 8 Bit parallel 80...

Page 37: ...ST7038 Ver 1 1 37 61 2007 01 25 l Intel 8051 interface Serial 4 line SPI l Intel 8051 interface Serial 3 line SPI l Intel 8051 interface Serial I 2 C ...

Page 38: ... end Wait time 32 4μS Wait time 32 4μS Wait time 200mS for power stable Bias Set Built in voltage follower circuit RS R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 1 BS2 BS1 OPF2 OPF1 ICON Power Ser RS R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 1 0 Ion Bon Ron Fon Wait time 32 4μS Function set RS R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 DL X X IS1 IS0 Power Contrast Set RS R W DB7 DB6 DB5 DB...

Page 39: ...ntrast set CALL WRINS_CHK CALL DELAY40uS MOV A 53H Power down Contrast set CALL WRINS_CHK CALL DELAY40uS MOV A 14H Bias Follwer set CALL WRINS_CHK CALL DELAY40uS MOV A 67H ICON Power B R F set CALL WRINS_CHK CALL DELAY200mS for power stable MOV A 0CH DISPLAY ON CALL WRINS_CHK CALL DELAY40uS MOV A 01H CLEAR DISPLAY CALL WRINS_CHK CALL DELAY2mS MAIN_START XXXX XXXX XXXX WRINS_CHK CALL CHK_BUSY WRINS...

Page 40: ... CALL WRINS_CHK CALL DELAY40uS MOV A 14H Bias Follwer set CALL WRINS_CHK CALL DELAY40uS MOV A 67H ICON Power B R F set CALL WRINS_CHK CALL DELAY200mS for power stable MOV A 0CH DISPLAY ON CALL WRINS_CHK CALL DELAY40uS MOV A 01H CLEAR DISPLAY CALL WRINS_CHK CALL DELAY2mS MAIN_START XXXX XXXX XXXX WRINS_CHK CALL CHK_BUSY WRINS_NOCHK PUSH A ANL A F0H CLR RS EX Port 3 0 CLR RW EX Port 3 1 SETB E EX Po...

Page 41: ...SET CALL WRINS_NOCHK 8 bit CALL DELAY40uS MOV A 7FH Contrast set CALL WRINS_NOCHK CALL DELAY40uS MOV A 53H Power down Contrast set CALL WRINS_NOCHK CALL DELAY40uS MOV A 14H Bias Follwer set CALL WRINS_NOCHK CALL DELAY40uS MOV A 67H ICON Power B R F set CALL WRINS_NOCHK CALL DELAY200mS for power stable MOV A 0CH DISPLAY ON CALL WRINS_NOCHK CALL DELAY40uS MOV A 01H CLEAR DISPLAY CALL WRINS_NOCHK CAL...

Page 42: ...HLS 1 l COM normal direction SEG reverse direction SHLC 1 SHLS 0 l COM reverse direction SEG normal direction SHLC 0 SHLS 1 l COM reverse direction SEG reverse direction SHLC 0 SHLS 0 3 Line Display Mode l COM normal direction SEG normal direction SHLC 1 SHLS 1 3 line x 16 characters SHLC 1 SHLS 1 l COM normal direction SEG reverse direction SHLC 1 SHLS 0 3 line x 16 characters SHLC 1 SHLS 0 ...

Page 43: ...1 1 43 61 2007 01 25 l COM reverse direction SEG normal direction SHLC 0 SHLS 1 3 line x 16 characters SHLC 0 SHLS 1 l COM reverse direction SEG reverse direction SHLC 0 SHLS 0 3 line x 16 characters SHLC 0 SHLS 0 ...

Page 44: ...ed l If the calculation value of V0 is higher than VOUT the real V0 value will saturate to VOUT l Internal built in booster can only be used when OPF1 0 OPF2 0 l To keep V0 level stable be sure the voltage level of VOUT is higher than V0 by at least 0 5V even displaying the heaviest loading pattern If the panel size is larger than 3 the recommend VOUT should be higher than V0 by at least 0 8V even...

Page 45: ...wer Furthermore the loading of built in Booster is increasing too That will cause the Booster efficiency drop and V0 maybe affected Referential Power Connection When using internal Booster Regulator and Follower the referential connection is shown below 2X Booster Regulator Follower ST7038 VSS VOUT CAP3P OPEN C1 CAP1P CAP1N C1 OPEN CAP2N CAP2P CAP4P OPEN V0 V1 V2 V3 V4 VSS VOP 1 8V 3 3V VDD VDD2 N...

Page 46: ...OUT V0 0 3 12 V LCD Driver Voltage Follower V1 V2 V3 V4 0 3 12 V Operating Temperature TOPR 30 85 o C Storage Temperature TSTO 65 150 o C System MPU Side ST7038 Chip Side VSS VDD VSS VDD V0 V4 VOUT VSS Notes 1 Stresses over the Limiting Values may cause permanent damage to the device 2 Parameters are valid over operating temperature range unless otherwise specified All voltages are relative to VSS...

Page 47: ...VDD VDD V Input Low Voltage Except OSC1 VIL1 0 3 0 2 VDD V Input High Voltage OSC1 VIH2 0 8 VDD VDD V Input Low Voltage OSC1 VIL2 0 2 VDD V Output High Voltage DB0 DB7 VOH1 IOH 1 5mA 1 4 V Output Low Voltage DB0 DB7 VOL1 IOL 2 0mA 0 66 V Common Resistance RCOM V0 4V Id 0 05mA 2 20 K Segment Resistance RSEG V0 4V Id 0 05mA 2 30 K Input Leakage Current ILEAK VDD 0V to VDD 1 1 A Pull Up MOS Current I...

Page 48: ...tup time RS tAW6 20 15 15 ns System cycle time E tCYC6 240 150 120 ns Data setup time tDS6 150 80 60 Data hold time tDH6 20 15 15 ns Access time tACC6 320 260 240 Output disable time D0 to D7 tOH6 200 130 100 ns Enable Rise Fall time tr tf 20 20 20 ns Enable H pulse time tEWH 210 120 90 ns Enable L pulse time E tEWL 30 30 30 ns Note All timing is specified using 20 and 80 of VDD as the reference ...

Page 49: ...Enable L pulse width WRITE tCCLW 180 140 110 Enable H pulse width WRITE tCCHW 20 20 20 ns Enable L pulse width READ tCCLR 180 140 110 Enable H pulse width READ D0 to D7 tCCHR 20 20 20 ns WRITE Data setup time tDS8 120 80 70 ns WRITE Data hold time WR tDH8 80 50 50 ns READ access time CL 100 pF Read tACC8 240 220 180 ns READ Output disable time CL 100 pF Read tOH8 120 100 80 ns Note All timing is s...

Page 50: ...Clock Period tSCYC 180 110 80 SCL H pulse width tSHW 70 40 40 SCL L pulse width SCL tSLW 80 50 40 ns Address setup time tSAS 10 10 10 Address hold time RS tSAH 60 40 30 ns Data setup time tSDS 20 20 20 Data hold time SI tSDH 10 10 10 ns tCSS 20 20 20 CS SCL time CSB tCSH 210 120 90 ns Note All timing is specified using 20 and 80 of VDD as the reference ...

Page 51: ...n Max Min Max Min Max Units Serial Clock Period tSCYC 200 100 80 SCL H pulse width tSHW 70 40 30 SCL L pulse width SCL tSLW 100 50 40 ns Data setup time tSDS 20 20 20 Data hold time SI tSDH 10 10 10 ns tCSS 70 40 20 CS SCL time CSB tCSH 200 100 80 ns Note All timing is specified using 20 and 80 of VDD as the reference ...

Page 52: ...time tSU DAT 300 200 100 ns Data hold time SDA tHD DAT 0 0 9 0 0 9 0 0 9 us SCL SDA rise time tr 300 300 300 SCL SDA fall time SCL SDA tf 300 300 300 ns Capacitive load represent by each bus line Cb 400 400 400 pf Setup time for a repeated START condition tSU STA 0 7 0 6 0 6 us Start condition hold time SDA tHD STA 0 6 0 6 0 6 us Setup time for STOP condition tSU STO 0 6 0 6 0 6 us Bus free time b...

Page 53: ...ST7038 Ver 1 1 53 61 2007 01 25 Hardware Reset XRESET ...

Page 54: ...the oscillation frequency is 284KHz 1 clock cycle time 3 52us 1 4 bias 1 9 duty 1 frame 14 08ms 71Hz SHLC 1 SHLS 1 1 2 3 4 7 8 1 2 3 4 7 8 1 2 3 4 7 8 COM2 V0 V1 V2 V3 V4 VSS COM1 V0 V1 V2 V3 V4 VSS COMI V0 V1 V2 V3 V4 VSS SEGx V0 V1 V2 V3 V4 VSS SEGx V0 V1 V2 V3 V4 VSS 1 Frame ...

Page 55: ...llation frequency is 249 7KHz 1 clock cycle time 4us 1 5 bias 1 17 duty 1 frame 14 42ms 69 36Hz SHLC 1 SHLS 1 V0 V1 V2 V4 VSS V3 V0 V1 V2 V4 VSS V3 V0 V1 V2 V4 VSS V3 V0 V1 V2 V4 VSS V3 V0 V1 V2 V4 VSS V3 1 2 3 4 ICON 15 16 1 2 3 4 ICON 15 16 1 2 3 4 ICON 15 16 COM2 COM1 COMI SEGx SEGx 1 Frame ...

Page 56: ...lation frequency is 370 5KHz 1 clock cycle time 2 70us 1 6 bias 1 25 duty 1 frame 14 04ms 71 25Hz SHLC 1 SHLS 1 V0 V1 V2 V4 VSS V3 V0 V1 V2 V4 VSS V3 V0 V1 V2 V4 VSS V3 V0 V1 V2 V4 VSS V3 V0 V1 V2 V4 VSS V3 1 2 3 4 ICON 23 24 1 2 3 4 ICON 23 24 1 2 3 4 ICON 23 24 COM2 COM1 COMI SEGx SEGx 1 Frame ...

Page 57: ...ST7038 Ver 1 1 57 61 2007 01 25 I O PAD CONFIGURATION Input PAD No Pull up RS R W XRESET CSB CLS PMOS NMOS PMOS NMOS Enable Data I O PAD DB0 DB7 PMOS NMOS PMOS VDD VDD VDD VDD ...

Page 58: ...ST7038 Ver 1 1 58 61 2007 01 25 APPLICATION CIRCUIT l 6800 series 8 bit Interface VSS VDD RST RS CSB DB3 DB2 DB1 DB0 E RW DB7 DB6 DB5 DB4 ...

Page 59: ...ST7038 Ver 1 1 59 61 2007 01 25 l 8080 series 8 bit Interface VSS VDD RST RS CSB DB3 DB2 DB1 DB0 RD WR DB7 DB6 DB5 DB4 ...

Page 60: ...ST7038 Ver 1 1 60 61 2007 01 25 l I 2 C Interface ...

Page 61: ...61 61 2007 01 25 Reversion History Version Date Description 1 0 2006 08 03 Release Version 1 1 2007 01 25 1 Modify minimum operation VDD range to 1 65V 2 Remove reversion history before Ver 1 0 3 Redraw Timing Figures ...

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