ST7038
Ver 1.1
14/61
2007/01/25
FUNCTION DESCRIPTION
MICROPROCESSOR INTERFACE
Chip Select Input
The CSB pin is used for chip selection. ST7038 can interface with an MPU when CSB is "L". When CSB is set to
“
H
”
, the
control signal inputs, A0, /RD(E) and /WR(R/W), are disabled and DB0 to DB7 are set to be high impedance. When using
3-line or 4-line serial interface, the internal shift register and counter are reset right after the falling edge of CSB.
Parallel / Serial Interface
ST7038 has five interface modes to interface with an MPU, which are three serial interfaces and two parallel interfaces.
These interface modes are selected by PS2~PS0 pins as shown below.
Table 1
Parallel / Serial Interface Modes
Parallel / Serial
PS2
PS1
PS0
CSB
Interface Mode
L
L
L
CSB
8000-series parallel MPU interface mode
Parallel
L
L
H
CSB
6880-series parallel MPU interface mode
L
H
L
CSB
4-line SPI (Serial Peripheral Interface) mode
L
H
H
CSB
3-line SPI (Serial Peripheral Interface) mode
Serial
H
L
L
--
I
2
C interface mode
Parallel Interface (PS[2:0] = "0, 0, X")
The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by PS0 as shown in Table 2. The
access type is determined by signals on A0, /RD(E) and /WR(R/W) as shown in Table 3.
Table 2
Microprocessor Selection in Parallel Interface
PS0
CSB
A0
/RD(E)
/WR(R/W)
DB0 to DB7
MPU Type
L
CSB
A0
/RD
/WR
DB0 to DB7
8080-series MPU
H
CSB
A0
E
R/W
DB0 to DB7
6800-series MPU
Table 3
Parallel Access
Common
6800-series MPU
8080-series MPU
A0
E
R/W
/RD
/WR
Description
H
H
H
L
H
Read display data
H
H
L
H
L
Write display data
L
H
H
L
H
Read status
L
H
L
H
L
Write register (instruction)
Note: By fixing the /RD(E) pin to
“
H
”
in 6800-series interface, the CSB pin can be used as the
“
Enable
”
signal. In this way, the
data is latched at the rising edge of CSB and the access type is determined by the signals A0 and /WR(R/W).
Serial Interface (3-Line / 4-Line / I
2
C)
The serial interface mode can be selected by PS2~PS0 as listed below:
Serial mode
PS2
PS1
PS0
CSB
A0
4-Line SPI mode
L
H
L
CSB
A0
3-Line SPI mode
L
H
H
CSB
Not used
I
2
C SPI mode
H
L
L
Not Used
Not Used
Note: Please connect the pins which are not used to
“
H
”
.
3-Line/4-Line SPI (PS[2:0] = "0, 1, X")
When CSB=
”
L
”
, ST7038 is active and the SI and SCL inputs are enabled. When CSB=
”
H
”
, ST7038 is inactive and the
internal 8-bit shift register and 3-bit counter are reset. The data/command indication is controlled via the software A0 bit (for
3-Line SPI) or the A0 Pin (for 4-Line SPI). For 4-Line SPI, A0=
”
H
”
indicates signal on data bus is display data while A0=
”
L
”
indicates signal on data bus is instruction. For 3-Line SPI, the first bit is A0 which indicates the following bits belong to display
data or instruction. Serial data will be latched on the rising edge of serial clock. The shift register will collect the serial bits and
reformat them to be an 8-bit parallel data at the 8th (4-Line SPI) or 9th (3-Line SPI) serial clock. The DDRAM column address
pointer will be increased by one automatically after the 8-bit data is transferred into the DDRAM. The read of data or status
(BF and AC) is not allowed in serial interface (neither 3-Line SPI nor 4-Line SPI).