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L6917B
LAYOUT GUIDELINES
Since the device manages control functions and high-current drivers, layout is one of the most important things
to consider when designing such high current applications.
A good layout solution can generate a benefit in lowering power dissipation on the power paths, reducing radi-
ation and a proper connection between signal and power ground can optimise the performance of the control
loops.
Integrated power drivers reduce components count and interconnections between control functions and drivers,
reducing the board space.
Here below are listed the main points to focus on when starting a new layout and rules are suggested for a cor-
rect implementation.
■
Power Connections.
These are the connections where switching and continuous current flows from the input supply towards the load.
The first priority when placing components has to be reserved to this power section, minimizing the length of
each connection as much as possible.
To minimize noise and voltage spikes (EMI and losses) these interconnections must be a part of a power plane
and anyway realized by wide and thick copper traces. The critical components, i.e. the power transistors, must
be located as close as possible, together and to the controller. Considering that the "electrical" components re-
ported in fig. 13 are composed by more than one "physical" component, a ground plane or "star" grounding con-
nection is suggested to minimize effects due to multiple connections.
Figure 13. Power connections and related connections layout guidelines (same for both phases)
Fig. 13a shows the details of the power connections involved and the current loops. The input capacitance
(CIN), or at least a portion of the total capacitance needed, has to be placed close to the power section in order
to eliminate the stray inductance generated by the copper traces. Low ESR and ESL capacitors (electrolytic or
Ceramic or both) are required.
■
Power Connections Related.
Fig.13b shows some small signal components placement, and how and where to mix signal and power ground
planes.
The distance from drivers and mosfet gates should be reduced as much as possible. Propagation delay times
R
F
R
F B
V
O SC
∆
⋅
V
IN
----------------------------------
ω
T
L
2
R
D R OO P
ESR
+
(
)
⋅
--------------------------------------------------------
5
4
---
⋅
⋅
⋅
=
C
F
C o
L
2
---
⋅
R
F
--------------------
=
V
IN
LOAD
HS
R
gat e
LS
R
gat e
HGATEx
PHASEx
LGATEx
PGNDx
C
IN
C
OUT
L
D
C
BOOTx
V
IN
LOAD
HS
LS
BOOTx
PHASEx
VCC
SGND
C
IN
C
OUT
L
D
+V
CC
C
VCC
a. PCB power and ground planes areas b. PCB small signal components placement
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