2.5
Status Model
2 – 15
2.5
Status Model
The SIM964 status registers follow the hierarchical IEEE–488.2 for-
mat. A block diagram of the status register array is given in Figure 2.1.
7
X
5
4
3
2
1
0
CESB
MSS
ESB
IDLE
undef
LLIM
ULIM
IOVLD
7
6
5
4
3
2
1
0
Status Byte
SB
SRE
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
OPC: Operation Complete
INP: Input Buffer Error
DDE: Device Error
EXE: Execution Error
CME: Command Error
URQ: User Request
PON: Power On
QYE: Query Error
ESR
ESE
Standard Event Status
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
PARITY: Parity Error
FRAME: Framing Error
HWOVRN: Hardware Overrun
OVR: Input Buffer Overrun
RTSH: RTS Halted
CTSH: CTS Halted
DCAS: Device Clear
NOISE: Noise Error
CESR
CESE
Communication Error Status
-STATUS
OVLD
ULCR
LLCR
Figure 2.1: Status Register Model for the SIM964.
There are three categories of registers in the SIM964 status model:
Condition Registers : These read-only registers correspond to the real-time condi-
tion of some underlying physical property being monitored.
Queries return the latest value of the property, and have no
other e
ff
ect. Condition register names typically end with
CR
(
OVLD
being an exception).
Event Registers : These read-only registers record the occurrence of defined
events. When the event occurs, the corresponding bit is set
to 1. Upon querying an event register, any set bits within it
are cleared. These are sometimes known as “sticky bits,” since
once set, a bit can only be cleared by reading its value. Event
register names end with
SR
.
Enable Registers : These read
/
write registers define a bitwise mask for their cor-
responding event register. If any bit position is set in an event
register while the same bit position is also set in the enable
register, then the corresponding summary bit message is set.
Enable register names end with
SE
.
SIM964
Analog Limiter
