PulseBlasterDDS-I-300
The PB Core controls the timing of the gating pulses and provides the necessary control signals for frequency, phase,
shape and amplitude registers. The PB Core also outputs TTL signals to the outside world, as programmed by the user.
The PB processor core executes instructions as written by the user and stored in the on-chip SRAM module, and, once
programmed, the processor operates autonomously.
The DDS and PB cores are driven from a common clock source (the 50 MHz
1
Reference Clock in Figure 1). The on-
board clock source is removable and, in lieu of the on-board clock, any 3.3 V TTL compatible clock source of arbitrary
stability can be used.
The DDS and PB cores have been integrated onto a single silicon chip. High performance DAC chip and high-current
output amplifier complement the design. User control of the system is provided through the host-programming interface
over the PCI bus or USB controller.
1
A 75 MHz clock may be used with the PulseBlasterDDS-I-300.
http://www.spincore.com
5
2017-11-14
Figure 1:
PulseBlasterDDS-I-300 Board Architecture.
