PulseBlasterDDS-I-300
3
END_LOOP
Address of beginning of loop
Specify end of a loop. Execution
returns to begging of loop and
decrements loop counter.
4
JSR
Address of first subroutine
instruction
Program execution jumps to
beginning of a subroutine
5
RTS
Unused
Program execution returns to
instruction after JSR was called
6
BRANCH
Address of instruction to skip to
Program execution continues at
specified instruction. This behaves like
the goto statement found in many
programming languages
7
LONG_DELAY
Number of desired loops. This
value must be greater than or equal to
2.
For long interval instructions.
Executes length of pulse given in the
time field multiplied by the value in the
data field.
8
WAIT
Unused
Program execution pauses and waits
for a software or hardware trigger to
resume it. The latency between a trigger
occurring and the program resuming is
the time used as the delay for the wait
instruction plus a fixed time of 6 clock
cycles.
Table 3
: PulseBlaster Instructions.
Control lines
To control the operation of the PulseBlasterDDS-I-300, each instruction in the pulse program specifies a flag word
which sets both the internal control lines and user programmable digital outputs. The control lines stay in the given state
for the duration of the instruction. The internal control lines are described below in Table 4.
Control Line
Function
frequency select
Selects between the 16 available frequency registers
4
TX
5
channel phase select
Selects between the 16 available phase registers
6
tx_enable
Enables TX output on the Analog Out connector. If this control line is disabled,
the Analog Out channel is turned off (zero output voltage).
phase_reset
When this control line is enabled, all DDS channels will be reset to their time=0
phase. For example, if a channel is set to use a phase register with 90deg, it will be
reset to the midpoint output level and stay that way until the phase reset control line
is disabled. This allows the the phase of pulses to be synchronized between scans.
Table 4:
Internal control lines.
4
Firmware design 10-16 has been modified to have 1024 available frequency registers.
5
TX refers to RF output.
6
Firmware design 10-16 has been modified to have 4 available phase registers.
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17
2017-11-14
