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Monaco Technical Reference

Spectrum Signal Processing

Registers

48

Part Number 500-00191

Revision 2.00

on reset.

BUSERRA

Status of the last bus cycle access made to the SCV64 by node A, including
SCV64 register and VME master accesses. Set to “1” if there was an error.
Cleared by writing “10h” to the VSTATUS register. All other interrupts are
cleared when the source of the interrupt is cleared. This interrupt is cleared
on reset.

KAVEC

Status of the interrupt vector last received on the data bus. High if the
vector was not valid. During the IACK cycle, a non-vectored interrupt
source causes this bit to be set, denoting a non-valid vector value on the
bus. This bit is cleared on reset. The next SCV64 register, IACK, or
VMEOUT cycle updates KAVEC. This signal is active high.

/KIPL2..0

The interrupt level of pending interrupts in the SCV64. These signals are
active low. For example, a value of 0x0 indicates that interrupt level 7 is
pending.

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Summary of Contents for Monaco Quad 'C6x VME64

Page 1: ...Monaco Quad C6x VME64 Board Technical Reference Document Number 500 00191 Revision 2 00 September 1999 ...

Page 2: ...ding those to reproduce this document or parts thereof in any form without permission in writing from Spectrum Signal Processing Inc All trademarks are registered trademarks of their respective owners Spectrum Signal Processing reserves the right to change any of the information contained herein without notice ...

Page 3: ...ignal com To help us assist you better and faster please have the following information ready A concise description of the problem The names of all Spectrum hardware components The names and version numbers of all Spectrum software components The minimum amount of code that demonstrates the problem The versions of all software packages including compilers and operating systems At Spectrum we know ...

Page 4: ... Technical Reference Spectrum Signal Processing Preface iv Part Number 500 00191 Revision 2 00 Rev Date Changes Section 2 00 Sept 1999 Updated for TMS320C6201B and TMS320C6701 DSPs n a Document Change History ...

Page 5: ...t Conditions 5 1 6 1 VME SYSRESET 5 1 6 2 VME A24 Slave Interface Reset 5 1 6 3 JTAG Reset 5 1 7 Board Layout 6 1 8 Jumper settings 7 2 Processor Nodes 9 2 1 Processor Memory Configuration 11 2 1 1 Internal Memory 11 2 1 2 External Memory 11 2 2 Synchronous Burst SRAM 15 2 3 Synchronous DRAM 15 2 4 Processor Expansion Module 15 2 5 Host Port 15 2 6 Interrupt Lines 15 2 7 Processor Booting 16 2 8 S...

Page 6: ...be Control Mode 30 5 3 Interface Signals 31 5 4 DSP LINK3 Reset 31 6 PCI Interface 33 6 1 Hurricane Configuration 33 6 2 Hurricane Implementation 36 7 JTAG Debugging 37 8 Interrupt Handling 39 8 1 Overview 39 8 2 DSP LINK3 Interrupts to Node A 40 8 3 PEM Interrupts 41 8 4 PCI Bus Interrupts 41 8 5 Hurricane Interrupt 41 8 6 SCV64 Interrupt 41 8 7 Bus Error Interrupts 43 8 8 Inter processor Interru...

Page 7: ...DSP LINK3 Register 54 ID Register 55 VME A24 Status Register 56 VME A24 Control Register 57 10 Specifications 59 10 1 Board Identification 59 10 2 General 60 10 3 Performance and Data Throughput 61 11 Connector Pinouts 63 11 1 VME Connectors 64 11 2 PMC Connectors 67 11 3 PEM Connectors 71 11 4 JTAG Connectors 73 ...

Page 8: ...Monaco Technical Reference Spectrum Signal Processing Table of Contents viii Part Number 500 00191 Revision 2 00 ...

Page 9: ... Processor Node Block Diagram 10 Figure 4 DSP Memory Map 13 Figure 5 DSP Memory Map for External Memory Space CE1 14 Figure 6 Serial Port Routing 17 Figure 7 Global Bus Arbitration 20 Figure 8 Primary VME A24 A32 Memory Map 24 Figure 9 A24 Secondary Interface Memory Map 25 Figure 10 PCI Memory Map 33 Figure 11 JTAG Chain 37 Figure 12 Interrupt Routing 40 Figure 13 Connector Layout 63 ...

Page 10: ...Monaco Technical Reference Spectrum Signal Processing Table of Contents x Part Number 500 00191 Revision 2 00 ...

Page 11: ...SP LINK3 Data Transfer Operating Modes 30 Table 11 Hurricane Register Set 34 Table 12 KIPL Status Bits and the IACK Cycle 42 Table 13 Register Address Summary 45 Table 14 Specifications 60 Table 15 Data Access Transfer Performance 61 Table 16 VME P1 Connector Pinout 64 Table 17 VME P2 Connector Pinout PMC to VME P2 65 Table 18 VME P2 Connector DSP LINK3 to VME P2 66 Table 19 PMC Connector JN1 Pino...

Page 12: ...Monaco Technical Reference Spectrum Signal Processing Table of Contents xii Part Number 500 00191 Revision 2 00 ...

Page 13: ...d point TMS320C6201 200 MHz Monaco67 Floating point TMS320C6701 167 MHz Both the Monaco and the Monaco67 are referred to as Monaco in this manual unless otherwise noted Monaco has the following features Up to four TMS320C6201 or TMS320C6701 processing nodes 128K x 32 bit of SBSRAM per processing node 4M x 32 bit of SDRAM per processing node Shared access to a 132 MBytes s PMC module site via the S...

Page 14: ...ge chip supports high speed data transfer from an on board PMC site to the shared memory The industry standard IEEE 1386 PMC module site allows developers to select from a wide variety of third party modules 1 2 3 PEM Four independent high speed full bandwidth bi directional dataflow channels between standard mezzanine boards Processor Expansion Modules or PEMs and the C6x processors are supported...

Page 15: ...om Spectrum DSP LINK3 Specification from Spectrum PEM Specification from Spectrum TMS320C6000 Peripherals Reference Guide from Texas Instruments SCV64 User Manual from Tundra Semiconductor Corporation Hurricane Data Sheet from Spectrum Draft Standard Physical and Environmental Layers for PCI Mezzanine Cards PMC IEEE P1386 1 Draft 2 0 available from IEEE VME64 ANSI VITA 1 1994 available from ANSI ...

Page 16: ... these sites must not exceed 5 Amps When adding modules to the Monaco board ensure that the power requirements for the modules are within the specified limits and that the system power supply and cooling are sufficient to meet the added requirements SBSRAM 128K x 32 Address Buffer and Data Latches Hurricane PMC Site Test Bus Controller VME P1 Connector SDRAM 4M x 32 DSP LINK3 Interface Node A C6x ...

Page 17: ...rface Y Y PMC interface Y Y DSP LINK3 interface Y Y 1 6 1 VME SYSRESET A VME SYSRESET is initiated when the SYSRESET line on the VME bus is driven low All devices and registers on the Monaco board are reset to their default conditions 1 6 2 VME A24 Slave Interface Reset The VME A24 slave interface reset is initiated from the VME bus by setting bit D0 of the VME A24 Control Register to 0 All device...

Page 18: ...ayout of the Monaco board PMC Site PEM Site Nodes A and B PEM Site Nodes C and D J3 JN4 VME P2 JN12 JN13 JN10 JN11 JN8 JN9 JN6 JN7 VME P1 Node D C6x Node C C6x Node B C6x Node A C6x J1 JTAG IN Connector J2 JTAG OUT Connector J8 DSP LINK3 Ribbon Cable Connector JN5 JN1 JN2 JP10 JP8 JP9 JP7 JP4 JP5 JP3 JP2 JP1 1 2 3 4 5 6 7 8 8 9 10 11 12 13 Figure 2 Board Layout ...

Page 19: ... base address bit A20 0 1 JP1 Pins 9 10 VME A24 slave interface base address bit A19 0 1 JP1 Pins 11 12 VME A24 slave interface base address bit A18 0 1 JP1 Pins 13 14 VME A24 slave interface base address bit A17 0 1 JP2 Node A boot mode PEM HPI JP3 Node B boot mode PEM HPI JP4 Node C boot mode PEM HPI JP5 Node D boot mode PEM HPI JP7 Node A Serial Port 1 Routing VME P2 PEM JP8 Node B Serial Port ...

Page 20: ...Monaco Technical Reference Spectrum Signal Processing Introduction 8 Part Number 500 00191 Revision 2 00 ...

Page 21: ...following figure Table 3 Processor Configurations Populated Configuration Node A Node B Node C Node D One Node Y Two Nodes Y Y Four Nodes Y Y Y Y Each DSP node consists of One TMS320C6201 DSP operating at 200 MHz for Monaco or one TMS320C6701 DSP operating at 167 MHz for Monaco67 128K of 32 bit Synchronous burst SRAM SBSRAM 4M of 32 bit Synchronous DRAM SDRAM Processor Expansion Module PEM interfa...

Page 22: ... 2 00 Node Local Resources C6x DSP 128K x 32 SBSRAM 4M x 32 SDRAM DSP Local Bus C6x Host Port Interface HPI Bus JTAG Test Bus Shared with Node Pair PEM Site DSP LINK3 Interface Node A Only Serial Port 1 Serial Port 0 Global Shared Bus Address Buffer and Data Latches Figure 3 Processor Node Block Diagram ...

Page 23: ...bytes These three regions define memory space which is implemented in the DSP processor 2 1 2 External Memory External memory is segmented into 4 regions external memory interface CE0 16 Mbytes external memory interface CE1 4 Mbytes external memory interface CE2 16 Mbytes external memory interface CE3 16 Mbytes External memory CE0 CE1 CE2 and CE3 consists of node local memory resources which are a...

Page 24: ...ld 2 cycles read setup 4 cycles read strobe 4 cycles read hold 1 cycle all cycles are clockout1 cycles EMIF CE2 Control Register 0x0180 0010 0xFFFF 3F33 MTYPE 32 bit wide SDRAM No other bits are used EMIF CE3 Control Register Used for PEM Must be reconfigured for individual PEM 0x0180 0014 0x72B7 0A23 MTYPE 32 bit wide asynchronous interface address 0x01800004 value 0x30E40421 MTYPE 32 bit wide as...

Page 25: ... KB 0140 0000 External Memory Space CE1 Upon Reset External Memory Space CE1 After TOUT0 is toggled PEM EEPROM Boot Mode DSP LINK3 Shared SRAM SCV64 Registers see the following CE1 memory map 4 MB 0180 0000 Internal Peripheral Space 2 MB 01A0 0000 Reserved 6 MB 0200 0000 Local SDRAM CE2 16 MB 0300 0000 Processor Expansion Module PEM CE3 16 MB 0400 0000 Reserved 2 GB 64 MB 8000 0000 Internal Data R...

Page 26: ...tandard Fast Access Reserved 0167 FFFC 0168 0000 DSP LINK3 RDY Controlled Access 016B FFFC 016C 0000 Hurricane Registers Hurricane Registers 016C 1FFC 016D 0000 Node A VPAGE Register Node B C or D VPAGE Register 016D 7FFC 016D 8000 Shared Bus Registers Shared Bus Registers 016D FFFC 016E 0000 SCV64 Register Set R W SCV64 Register Set R W 016E 7FFC 016E 8000 Reserved Reserved 016E FFFC 016F 0000 IA...

Page 27: ...th a pair of connectors for each DSP While both DSP devices share the same PEM the two DSP buses are kept separate to allow very fast PEM data transfer rates The PEM is capable of booting the DSPs from local ROM with up to 4 MBytes of addressable boot space available to each DSP Refer to the PEM Specification for mechanical and functional details of the PEM interface 2 5 Host Port A separate A24 V...

Page 28: ...t JP2 Node A IN OUT JP3 Node B IN OUT JP4 Node C IN OUT JP5 Node D IN OUT The Monaco board uses the CE1 memory space of the C6x memory map 1 for the boot space upon power up or reset Immediately after booting the C6x cannot access the resources in its CE1 space such as the Hurricane registers Global Shared SRAM and SCV64 Registers In order to access these CE1 resources the C6x must toggle the stat...

Page 29: ...he PEM connector associated with the DSP node Serial Port routing for the Monaco board is shown the figure Complete pinouts for the connectors are given in the Connector Pinouts chapter PMC Connector JN5 Node D Serial Port 0 Node C Serial Port 0 Node B Serial Port 0 Node A Serial Port 0 Node D C6x Serial Port 0 Serial Port 1 Node C C6x Serial Port 0 Serial Port 1 Node B C6x Serial Port 0 Serial Po...

Page 30: ... port routing jumper corresponding to the node J7 J8 J9 or J10 must be OUT for port 1 to be routed to the node s PEM 2 connector Table 7 VME and PMC Connections for Serial Port 1 Node A J7 IN Node B J8 IN Node C J9 IN Node D J10 IN Signal PMC JN5 VME P2 PMC JN5 VME P2 PMC JN5 VME P2 PMC JN5 VME P2 CLKS External clock 1 D 4 21 D 18 2 Z 3 22 Z 17 CLKR Receive clock 5 D 6 25 D 20 6 Z 5 26 Z 19 CLKX T...

Page 31: ...A access only No Access SCV64 Registers R W No Access No Access Global Shared Bus Registers R W No Access No Access VMEbus as master R W No Access 3 1 Memory 512K of 32 bit Asynchronous RAM implemented in four 512K x 8 bit Asynchronous RAM devices is provided on the Global Shared Bus The C6x DSPs can only perform 32 bit accesses to the Global Shared RAM Byte accesses are not supported 3 2 Arbitrat...

Page 32: ... Access to the Global Shared Bus can use single burst or locked cycles 3 2 1 Single Cycle Bus Access For single cycle accesses a device requests the global shared bus by simply initiating a read or write access to the bus When the bus is free the device acquires it and performs the single cycle access The bus is then released 3 2 2 Burst Cycle Bus Access Burst cycles are used during DMA transfers ...

Page 33: ...odify write accesses to the Global Shared RAM and registers It is highly recommended that Bus locking not be used It can lead to a deadlock condition and in particular result in debugger timeouts The following precautions should be observed when locking the Global Shared Bus 1 VME bus timeouts can occur because the SCV64 cannot access the board while a C6x has locked the bus 2 If node A accesses t...

Page 34: ...Monaco Technical Reference Spectrum Signal Processing Global Shared Bus 22 Part Number 500 00191 Revision 2 00 ...

Page 35: ...nnector The board may be installed in either a 5 row VME backplane or a 3 row backplane The two additional rows on the VME P2 connector Z and D only serve to route serial port signals from DSP processor nodes A B C and D to the VME backplane if the board is configured for that option Note If the Monaco board is installed in a 3 row VME chassis serial port routing will be restricted to the PEM and ...

Page 36: ... the SCV64 base address registers Only SCV64 A21 and A20 are used for decode on SCV64 VME slave accesses to the board D16 and D08E0 writes are not supported on the primary A32 A24 interface 4 3 A24 Secondary Slave Interface Jumper block JP1 sets address bits A23 A17 of the VME A24 slave interface This base address defines a 128K byte addressed memory space accessed by the VME bus Access to this sp...

Page 37: ...s 00 5FFFh 00 6000h Reserved 00 FFFFh 01 0000h Node A HPID DMA Space HPIA incremented all addresses mapped to 00 2008h 16 KB 01 3FFCh 01 4000h Node B HPID DMA Space HPIA incremented all addresses mapped to 00 3008h 16 KB 01 3FFCh C6x 01 B000h Node C HPID DMA Space HPIA incremented all addresses mapped to 00 4008h 16 KB 01 3FFCh 01 C000h Node D HPID DMA Space HPIA incremented all addresses mapped t...

Page 38: ...Node A Node B Node C Node D Description HPIC 00 2000h 00 3000h 00 4000h 00 5000h State for reading setting the Control Register value HPIA 00 2004h 00 3004h 00 4004h 00 5004h Used to read set the HPI address pointer The HPIA points into the C6x memory space HPID 00 2008h 00 3008h 00 4008h 00 5008h A VME host reads and writes data to this address for DMA transfers to the HPID register The HPIA regi...

Page 39: ... 4 4 Master A32 A24 A16 SCV64 Interface As a VME master the Monaco board supports A16 A24 or A32 transactions from any node to the VME64 bus through the SCV64 chip Any node can program the SCV64 s DMA Controller for VME Master Accesses and can directly master the VMEbus Each node has its own VPAGE Register to support the KFC KSIZE and upper 12 and lower 2 address bits to the SCV64 The upper 11 bit...

Page 40: ...Monaco Technical Reference Spectrum Signal Processing VME64 Bus Interface 28 Part Number 500 00191 Revision 2 00 ...

Page 41: ...access is interleaved within global shared SRAM accesses node A acquires the Global Shared Bus performs the SRAM access releases the Global Shared Bus performs the DSP LINK3 access acquires the Global Shared Bus and then performs the next Global Shared Bus SRAM access using a control register 5 1 DSP LINK3 Data Transfer Operating Modes The Monaco board supports four data transfer operating modes S...

Page 42: ...the DSP LINK3 data lines It determines which address page is accessed on the slave board This allows access to up to 2 14 address pages with each address page having an address depth of 2 14 The ASTRB Cycle has the same timing as the Standard Fast transfer cycle Ready Control Access 0168 0000h x For DSP LINK3 slave boards that require variable length access times DSTRB is active until the slave as...

Page 43: ...te ready RDY input 4 open collector interrupt inputs IRQ0 to IRQ3 These interrupt are logically OR ed and routed to the INT7 line of node A s C6x Refer to DSP LINK3 specification for details available from Spectrum s internet web site at http www spectrumsignal com 5 4 DSP LINK3 Reset Bit D0 of the DSP LINK3 register controls the DSP LINK3 reset line This register is located at address 016D 8018h ...

Page 44: ...Monaco Technical Reference Spectrum Signal Processing DSP LINK3 Interface 32 Part Number 500 00191 Revision 2 00 ...

Page 45: ...tly in use then it will be granted the bus It is up to the bus ownership timers of the Hurricane and PMC devices to prevent bus hogging PMC modules can directly master the Global Shared SRAM The memory map of the Monaco seen by a PMC module is shown in the following figure PCI Offset Address Access 0000 0000h Global Shared SRAM 001F FFFFh 0020 0000h Hurricane Control Registers 002F FFFFh 0030 0000...

Page 46: ...0000 0000 0x11 0x016C 0044 0x0020 0044 0x0020 0044 DPA PCI Address 0x0000 0000 0x12 0x016C 0048 0x0020 0048 0x0020 0048 DLNGTH Length 0x0000 0000 0x13 0x016C 004C 0x0020 004C 0x0020 004C DINTP Interrupt Point 0x0000 0000 Y 0x14 0x016C 0050 0x0020 0050 0x0020 0050 DSTRD DSP Stride 0x0000 0000 0x15 0x016C 0054 0x0020 0054 0x0020 0054 DPC Packet Control 0x0000 00F6 Y 0x16 0x016C 0058 0x0020 0058 0x00...

Page 47: ...formation 0x0000 0000 0x37 0x016C 00DC 0x0020 00DC 0x0020 00DC BMI7 Bank 7 Mapping Information 0x0000 0000 0x38 0x016C 00E0 0x0020 00E0 0x0020 00E0 BMI8 Bank 8 Mapping Information 0x0000 0000 0x39 0x016C 00E4 0x0020 00E4 0x0020 00E4 CSCR Cycle select all banks 0x0000 0000 Y 0x3A 0x016C 00E8 0x0020 00E8 0x0020 00E8 MABE CSER BER Map Bank Enable Chip Select Enable Mask Broadcast 0x0001 0100 Y 0x3B 0...

Page 48: ...ter 0xFF00 0000 Y 6 2 Hurricane Implementation The Hurricane PCI to DSP Bridge Data Sheet should be read in order to understand how it is used with the Monaco board On the DSP port of the Hurricane only bank 0 is used to access the Global Shared Bus All other Hurricane DSP banks are unused There are two devices on the PMC site s PCI bus the Hurricane chip and the PMC device The IDSEL line from eac...

Page 49: ... computer is supported through the JTAG IN connector If a JTAG IN connection with a clock signal is present the Test Bus Controller is automatically disconnected JTAG data lines are routed to each available C6x node The full JTAG chain is shown in the following diagram Unpopulated processor nodes are bypassed The JTAG IN input is buffered to reduce the load on an external JTAG device The JTAG OUT ...

Page 50: ...nected to the JTAG IN of the first board The JTAG OUT of the first board should be connected to the JTAG IN of second board The JTAG OUT of the second board should be connected to the JTAG IN of third board and so on The JTAG OUT connector of the last board is not connected to anything Note All hardware must be powered off before the JTAG cable are connected and the JTAG chain is set up ...

Page 51: ... has four interrupt pins which are configurable as either leading or falling edge triggered interrupts For the Monaco board all C6x interrupts are configured as rising edge triggered interrupts The NMI interrupts for the C6x DSPs are not used they are tied high The following block diagram shows how interrupts are routed to these pins on the Monaco board ...

Page 52: ... INT2 PEM INT1 PEM INT2 PEM INT1 PEM INT2 INT 7 INT 6 INT 5 INT 4 Node A C6x INT 7 INT 6 INT 5 INT 4 INT 7 INT 6 INT 5 INT 4 INT 7 INT 6 INT 5 INT 4 INT0 INT1 INT2 INT3 DSP LINK3 Interface Interrupts Node B C6x Node C C6x Node D C6x PCI Interrupt PCI Interrupt PCI Interrupt PCI Interrupt PCI Bus Interrupts INTA INTB INTC INTD Hurricane SCV64 Interrupt BUSERR_D VINTD BUSERR_C VINTC BUSERR_B VINTB B...

Page 53: ... OR gate The interrupt is not latched and its source must be cleared on the PMC module 8 5 Hurricane Interrupt The interrupt signal from the Hurricane chip is routed to each of the board s C6x processors On node A the PCI bus interrupt is also shared with the Hurricane interrupt on INT5 of the C6x through an OR gate For nodes B C and D the Hurricane interrupt is routed to INT7 of the C6x 8 6 SCV64...

Page 54: ...st be initialized in the following way KADDR0 bit D0 is set to 0 The value of the KIPL0 bit in the VSTATUS Register is inverted and placed in the KADDR1 bit bit D1 KSIZE0 bit D2 is set to 1 KSIZE1 bit D3 is set to 0 All three KFC bits bits D 6 4 are set to 1 The KIPL 2 1 status bits D 2 1 in the VSTATUS Register determine the offset of the address to read within the IACK cycle space KIPL2 is inver...

Page 55: ...t vector or to 1 if the value is not a valid interrupt vector Auto vectored interrupt sources can be cleared by accessing the SCV64 register set Refer to the SCV64 User Manual for more information 8 7 Bus Error Interrupts Bus error interrupts BUSERR_x are generated whenever an access cycle from a node or SCV64 DMA to the VME bus causes the SCV64 to generate a bus error This interrupt is routed onl...

Page 56: ...ocessors Node C for example can interrupt node B by writing 1 to the VINTB Register address 016D 8008h The VSTATUS Register address 016D 8000h also indicates that a node has a pending interrupt whenever any of the following bits is set to 1 Bit Interrupted Node D8 Node A D9 Node B D10 Node C D11 Node D A processor clears an interrupt by clearing its corresponding bit VINTx register In the case whe...

Page 57: ...TBC The following table summarizes the registers described in this section Table 13 Register Address Summary Register Access Privilege Bus Address VPAGE Register for node A R W Node A only 016D 0000h VPAGE Register for node B R W Node B only 016D 0000h VPAGE Register for node C R W Node C only 016D 0000h VPAGE Register for node D R W Node D only 016D 0000h VSTATUS Register R W All nodes 016D 8000h...

Page 58: ... address bits of the C6x to the full 32 bits of the VME address space This allows a C6x access the entire VME bus as a master by setting these bits to 1 Mbyte region being accessed A write to this register latches data lines D19 8 and presents them to the SCV64 upper address lines KADDR31 20 respectively For example a write to the VPAGE register with data equal to 8 0000h causes the next outbound ...

Page 59: ...ined interrupt to node A Set to 1 when another processor has set the VINTA interrupt register Active High BUSERRD Status of the last bus cycle access made to the SCV64 by node D including SCV64 register and VME master accesses Set to 1 if there was an error Cleared by writing 80h to the VSTATUS register All other interrupts are cleared when the source of the interrupt is cleared This interrupt is ...

Page 60: ... the interrupt is cleared This interrupt is cleared on reset KAVEC Status of the interrupt vector last received on the data bus High if the vector was not valid During the IACK cycle a non vectored interrupt source causes this bit to be set denoting a non valid vector value on the bus This bit is cleared on reset The next SCV64 register IACK or VMEOUT cycle updates KAVEC This signal is active high...

Page 61: ...Register Address 016D 8004h D31 D8 Reserved D7 D1 D0 Reserved Interrupt This register allows any processor to generate or clear an interrupt to node A Upon reset this value is 0 To generate an interrupt to node A set bit D0 of this register to 1 To clear an interrupt to node A set bit D0 of this register to 0 ...

Page 62: ...Register Address 016D 8008h D31 D8 Reserved D7 D1 D0 Reserved Interrupt This register allows any processor to generate or clear an interrupt to node B Upon reset this value is 0 To generate an interrupt to node B set bit D0 of this register to 1 To clear an interrupt to node B set bit D0 of this register to 0 ...

Page 63: ...Register Address 016D 800Ch D31 D8 Reserved D7 D1 D0 Reserved Interrupt This register allows any processor to generate or clear an interrupt to node C Upon reset this value is 0 To generate an interrupt to node C set bit D0 of this register to 1 To clear an interrupt to node C set bit D0 of this register to 0 ...

Page 64: ...Register Address 016D 8010h D31 D8 Reserved D7 D1 D0 Reserved Interrupt This register allows any processor to generate or clear an interrupt to node D Upon reset this value is 0 To generate an interrupt to node D set bit D0 of this register to 1 To clear an interrupt to node D set bit D0 of this register to 0 ...

Page 65: ...s do not affect the individual KBERR interrupt bits KIPL_END When set to 1 interrupts to node D that are generated from the SCV64 KIPL lines are enabled Active high KIPL_ENC When set to 1 interrupts to node C that are generated from the SCV64 KIPL lines are enabled Active high KIPL_ENB When set to 1 interrupts to node B that are generated from the SCV64 KIPL lines are enabled Active high KIPL_ENA ...

Page 66: ... Setting this bit D0 to 1 asserts reset to the DSP LINK3 Setting this bit D0 to 0 releases the DSP LINK3 from reset Set to 1 upon reset Application code must set it to 0 to release the DSP LINK3 from reset ASTRB_EN Setting this bit D1 to 1 enables ASTRB accesses to DSP LINK3 Accesses to the standard fast region when ASTRB_EN is set will be ASTRB accesses Setting this bit D1 to 0 disables ASTRB acc...

Page 67: ...l four bits but can only write to its own bit To identify its processor the DSP program first locks the Global Shared Bus for its use by asserting TOUT0 It then reads the value of this register and stores the result This value is toggled inverted and written back to the register The register is read once again and compared to the first reading to determine which bit was changed by the write operat...

Page 68: ...f the bit is simply a reflection of the HINT bit value in the corresponding C6x HPIC register A 1 in the bit position indicates that the corresponding C6x processor has requested an interrupt HINT_A Bit D0 is set to 1 when node A is requesting a host interrupt HINT_B Bit D1 is set to 1 when node B is requesting a host interrupt HINT_C Bit D2 is set to 1 when node C is requesting a host interrupt H...

Page 69: ...e Address 1004h D31 D8 Reserved D7 D1 D0 Reserved Reset The VME host uses this register to reset all Monaco board devices except for the SCV64 bus interface chip To reset the board the VME host writes a 0 to bit D0 This read write register is accessed from the VME A24 bus It is located at offset 1004h from the base address set by jumper JP1 A23 A17 ...

Page 70: ...Monaco Technical Reference Spectrum Signal Processing Registers 58 Part Number 500 00191 Revision 2 00 ...

Page 71: ...arlier DSP Monaco67 Monaco67 boards use the TMS320C6701 DSP The processor type and version can be identified by examining the DSPs on the board earlier DSPs have the marking C21 while TMS320C6201B chips are marked C31 Boards equipped with earlier TMS320C6201 revision 2 1 chips may also have heat sinks or fans attached to the cover of the DSPs The board s 600 level part number may also be used to d...

Page 72: ...2 General Table 14 Specifications Parameter Monaco TMS320C6201B Monaco TMS320C6201 Monaco67 TMS320C6701 Current Consumption 5 Volts 3 6 Amps 8 8 Amps 3 0 Amps 12 Volts 0 Amps 0 Amps 0 Amps 12 Volts 0 Amps 0 Amps 0 Amps Power 18 Watts 44 Watts 15 Watts Height 6U Width 1 VME slot Operating Temperature 0 C to 50 C ...

Page 73: ...SRAM read 88 74 MB s Global SRAM write 100 83 MB s DSP LINK3 Standard 15 12 5 MB s DSP LINK3 Standard Fast 28 24 MB s Hurricane Registers 115 138 ns VMEbus master read 2 MB s Coupled read Typical value for a real slave which is slower than for an ideal VME slave VMEbus master write 9 MB s De coupled write Typical value for a real slave which is slower than for an ideal VME slave VME Host Global SR...

Page 74: ...Monaco Technical Reference Spectrum Signal Processing Specifications 62 Part Number 500 00191 Revision 2 00 ...

Page 75: ...6x Node B C6x Node A C6x J1 JTAG IN Connector J2 JTAG OUT Connector J8 DSP LINK3 Ribbon Cable Connector JN5 JN1 JN2 PEM 1 PEM 2 PEM 1 PEM 2 PEM 1 PEM 2 PEM 1 PEM 2 Node D Node C Node B Node A 2 14 13 1 2 14 13 1 1 2 67 68 1 2 63 64 59 60 59 60 59 60 1 2 59 60 1 2 59 60 1 2 59 60 1 2 1 2 59 60 1 2 59 60 1 2 1 2 C B A 1 C B A 32 D C B A Z 1 D C B A Z 32 1 2 49 50 1 2 63 64 1 2 63 64 Figure 13 Connec...

Page 76: ... Table 16 VME P1 Connector Pinout Pin A Row Signal B Row Signal C Row Signal 1 D00 BBSY D08 2 D01 BCLR D09 3 D02 ACFAIL D10 4 D03 BG0IN D11 5 D04 BG0OUT D12 6 D05 BG1IN D13 7 D06 BG1OUT D14 8 D07 BG2IN D15 9 GND BG2OUT GND 10 SYSCLK BG3IN SYSFAIL 11 GND BG3OUT BERR 12 DS1 BR0 SYSRESET 13 DS0 BR1 LWORD 14 WRITE BR2 AM5 15 GND BR3 A23 16 DTACK AM0 A22 17 GND AM1 A21 18 AS AM2 A20 19 GND AM3 A19 20 I...

Page 77: ...21 GND 12 GND PMC JN4 24 GND PMC JN4 23 DX_A1 13 FSR_C1 PMC JN4 26 5V PMC JN4 25 GND 14 GND PMC JN4 28 D16 PMC JN4 27 FSR_A1 15 FSX_C1 PMC JN4 30 D17 PMC JN4 29 GND 16 GND PMC JN4 32 D18 PMC JN4 31 FSX_A1 17 CLKS_D1 PMC JN4 34 D19 PMC JN4 33 GND 18 GND PMC JN4 36 D20 PMC JN4 35 CLKS_B1 19 CLKR_D1 PMC JN4 38 D21 PMC JN4 37 GND 20 GND PMC JN4 40 D22 PMC JN4 39 CLKR_B1 21 CLKX_D1 PMC JN4 42 D23 PMC J...

Page 78: ...30 NC DR_A1 11 DX_C1 DL3_DSTRB A31 NC GND 12 GND DL3_ASTRB GND NC DX_A1 13 FSR_C1 DL3_RDY 5V NC GND 14 GND DL3_INT0 D16 DL3_INT2 FSR_A1 15 FSX_C1 DL3_INT1 D17 DL3_INT3 GND 16 GND NC D18 NC FSX_A1 17 CLKS_D1 DL3_D31 D19 DL3_D30 GND 18 GND DL3_D29 D20 DL3_D28 CLKS_B1 19 CLKR_D1 DL3_D27 D21 DL3_D26 GND 20 GND DL3_D25 D22 DL3_D24 CLKR_B1 21 CLKX_D1 DL3_D23 D23 DL3_D22 GND 22 GND DL3_D21 GND DL3_D20 CL...

Page 79: ... 12V 3 GND 4 INTA 5 INTB 6 INTC 7 BMODE1 8 5V 9 INTD 10 RSVD 11 GND 12 RSVD 13 CLK 14 GND 15 GND 16 GNT 17 REQ 18 5V 19 V I O 20 AD31 21 AD28 22 AD27 23 AD25 24 GND 25 GND 26 BE3 27 AD22 28 AD21 29 AD19 30 5V 31 V I O 32 AD17 33 FRAME 34 GND 35 GND 36 IRDY 37 DEVSEL 38 5V 39 GND 40 LOCK 41 SDONE 42 SBO 43 PAR 44 GND 45 V I O 46 AD15 47 AD12 48 AD11 49 AD9 50 5V 51 GND 52 BE0 53 AD6 54 AD5 55 AD4 5...

Page 80: ...D 11 BMODE2 12 3 3V 13 RST 14 BMODE3 15 3 3V 16 BMODE4 17 RSVD 18 GND 19 AD30 20 AD29 21 GND 22 AD26 23 AD24 24 3 3V 25 IDSEL 26 AD23 27 3 3V 28 AD20 29 AD18 30 GND 31 AD16 32 BE2 33 GND 34 RSVD 35 TRDY 36 3 3V 37 GND 38 STOP 39 PERR 40 GND 41 3 3V 42 SERR 43 BE1 44 GND 45 AD14 46 AD13 47 GND 48 AD10 49 AD8 50 3 3V 51 AD7 52 RSVD 53 3 3V 54 RSVD 55 RSVD 56 GND 57 RSVD 58 RSVD 59 GND 60 RSVD 61 ACK...

Page 81: ...7 14 P2A7 15 P2C8 16 P2A8 17 P2C9 18 P2A9 19 P2C10 20 P2A10 21 P2C11 22 P2A11 23 P2C12 24 P2A12 25 P2C13 26 P2A13 27 P2C14 28 P2A14 29 P2C15 30 P2A15 31 P2C16 32 P2A16 33 P2C17 34 P2A17 35 P2C18 36 P2A18 37 P2C19 38 P2A19 39 P2C20 40 P2A20 41 P2C21 42 P2A21 43 P2C22 44 P2A22 45 P2C23 46 P2A23 47 P2C24 48 P2A24 49 P2C25 50 P2A25 51 P2C26 52 P2A26 53 P2C27 54 P2A27 55 P2C28 56 P2A28 57 P2C29 58 P2A2...

Page 82: ...7 GND 8 GND 9 CLKX_A1 10 CLKX_C1 11 DR_A1 12 DR_C1 13 DX_A1 14 DX_C1 15 FSR_A1 16 FSR_C1 17 FSX_A1 18 FSX_C1 19 GND 20 GND 21 CLKS_B1 22 CLKS_D1 23 GND 24 GND 25 CLKR_B1 26 CLKR_D1 27 GND 28 GND 29 CLKX_B1 30 CLKX_D1 31 DR_B1 32 DR_D1 33 DX_B1 34 DX_D1 35 FSR_B1 36 FSR_D1 37 FSX_B1 38 FSX_D1 39 GND 40 GND 41 Reserved 42 Reserved 43 Reserved 44 Reserved 45 Reserved 46 Reserved 47 Reserved 48 Reserv...

Page 83: ...al Pin Signal 1 32MHz 2 GND 3 EA2 4 ED16 5 EA3 6 ED17 7 EA4 8 ED18 9 EA5 10 ED19 11 EA6 12 ED20 13 EA7 14 ED21 15 EA8 16 ED22 17 EA9 18 ED23 19 GND 20 GND 21 EA10 22 ED24 23 EA11 24 ED25 25 EA12 26 ED26 27 EA13 28 ED27 29 EA14 30 ED28 31 EA15 32 ED29 33 EA16 34 ED30 35 EA17 36 ED31 37 3 3V 38 5V 39 3 3V 40 5V 41 EA18 42 CLKX0 43 EA19 44 FSX0 45 ARE 46 DX0 47 ARDY 48 DR0 49 PEM_CE1 50 FSR0 51 AWE 5...

Page 84: ...D2 9 DR1 10 ED3 11 FSR1 12 ED4 13 CLKR1 14 ED5 15 GND 16 ED6 17 CLKS1 18 ED7 19 RSVD 20 GND 21 PEM_CE2 22 ED8 23 RSVD 24 ED9 25 HOLD 26 ED10 27 HOLDA 28 ED11 29 RSVD 30 ED12 31 EA20 32 ED13 33 EA21 34 ED14 35 RSVD 36 ED15 37 3 3V 38 5V 39 3 3V 40 5V 41 BE0 42 DMAC0 43 BE1 44 DMAC1 45 BE2 46 DMAC2 47 BE3 48 12V 49 SDRAS 50 12V 51 SDCAS 52 PEM_INT2 53 SDWE 54 RSVD 55 GND 56 GND 57 PEM_TIMER 58 RSVD ...

Page 85: ...ors use 2 x 7 0 1 x 0 1 bare pin headers Table 25 JTAG IN Connector Pinout Pin Signal Pin Signal 1 TMS 2 TRST 3 TDI 4 GND 5 PD 6 key no pin 7 TDO 8 GND 9 TCK_RET 10 GND 11 TCK 12 GND 13 EMU0 14 EMU1 Table 26 JTAG OUT Connector Pin Signal Pin Signal 1 TMS 2 TRST 3 TDO 4 key no pin 5 PD 6 GND 7 TDI 8 GND 9 TCK_RET 10 GND 11 TCK 12 GND 13 EMU0 14 EMU1 ...

Page 86: ...Monaco Technical Reference Spectrum Signal Processing Connector Pinouts 74 Part Number 500 00191 Revision 2 00 ...

Page 87: ...0h VMEbus VSB Bus Select 00000000h 016E 0024h VMEbus Interrupter Vector 00000000h 016E 0028h Access Protect Boundary 00000000h 016E 002Ch Tx FIFO Data Output Latch Read only 016E 0030h Tx FIFO Address Output Latch Read only 016E 0034h Tx FIFO AM Code and Control Bit Latch Read only 016E 0038h Location Monitor FIFO Read Port Read only 016E 003Ch SCV64 Mode Control 24000005h 016E 0040h Slave A64 Bas...

Page 88: ... Register 000000A8h 016E 00BCh Local Interrupts 5 and 4 Control Register 000000CBh 016E 00C0h Miscellaneous control register 00000000h 016E 00C4h Delay line control register Dynamically configured by SCV64 initialization routine 016E 00C8h Delay line status register 1 Dynamically configured by SCV64 initialization routine 016E 00CCh Delay line status register 2 Dynamically configured by SCV64 init...

Page 89: ... C C6x See DSP CE1 external memory space 14 chain JTAG 37 clear interrupt to node A 49 to node B 50 to node C 51 to node D 52 clock speed 1 configurations DSP processor 9 configuring Hurricane 33 connector 63 JTAG 73 IN 73 OUT 73 layout 63 PEM 71 PEM 1 71 PEM 2 72 PMC 67 JN1 67 JN2 68 JN4 69 JN5 70 VME P1 64 P2 DSP LINK3 to VME 66 PMC to VME 65 D data throughput specifications 61 data transfer ope...

Page 90: ...26 HPI See Host Port Interface Hurricane 33 configuring 33 implementation 36 interrupts 41 register set 34 I ID register 55 identifying processor the software is running on 55 IDSEL line 36 INT4 interrupt identify source 47 interface DSP LINK3 29 PCI 33 signals DSP LINK3 31 internal memory space of DSP 11 internal peripheral register values C6x 12 inter processor interrupts 44 interrupt bus error ...

Page 91: ...erformance specifications 61 pinout See connector PMC 2 connector 67 JN1 67 JN2 68 JN4 69 JN5 70 power supply 4 processor See DSP Processor Expansion Module See PEM R reference documents 3 register 45 address summary 45 C6x internal peripheral 12 DSP LINK3 54 Host Port Interface addresses 26 Hurricane register set 34 ID 55 KIPL enable 53 SCV64 VME64 75 VINTA 49 VINTB 50 VINTC 51 VINTD 52 VME A24 c...

Page 92: ...MS320C6201 1 9 TMS320C6701 1 9 token passing 19 TOUT0 16 21 V VINTA register 49 VINTB register 50 VINTC register 51 VINTD register 52 VME 2 A24 control register 57 A24 slave interface base address setting via jumpers 7 A24 slave interface reset 5 A24 status register 56 bus backplane connectors 23 interface 23 SCV64 VME64 master 27 primary slave 23 secondary slave 24 operation 23 connector P1 64 P2...

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