SOYO SY-7SBB, User Manual, Page: 51 / 76

BIOS Setup Utility SY-7SBB
47
3-4.1 CHIPSET FEATURES SETUP
CHIPSET
FEATURES Setting Description Note
Disabled
Auto
Configuration
Enabled It is strongly recommended to
enable this option so that the
system automatically sets all
chipset feature options on the
left panel of the screen (except
for cache update & BIOS
cacheable). Default
RAS Pulse Width
Refresh
6T
3T,4T,5T
,7T
The system designer must
select the number of CPU
clock
RAS Precharge Time
4T
2T,3T,5T
The precharge time is the
number of cycles it takes for
the RAS to accumulate its
charge before DRAM refresh.
If insufficient time is allowed,
refresh may be incomplete and
the DRAM may fail to retain
data.
RAS to CAS Delay 4T
2T,3T,5T
When DRAM is refreshed,
both rows and columns are
addressed separately. This
setup item allows you to
determine the timing of the
transition from RAS (row
address strobe) to CAS
(column address strobe).
Disabled
CPU to PCI Post
Write
Enabled Select enabled to use a fast
buffer for posting writes to
memory. Using a fast buffer
releases the CPU before
completion of a write cycle to
DRAM. Default