Sony XES-Z50, Service Manual

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IC102, 202 HM51W4260CLTT-7
– DSP Board –
256K MEMORY
ARRAY MAT
ROW
DECODER
256K MEMORY
ARRAY MAT
ROW
DECODER
PERIPHERAL
CIRCUIT
1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 21 22
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
ADDRESS BUS
ADDRESS BUS
I/O BUS
I/O BUFFER
SELECTOR
SELECTOR
I/O BUFFER
I/O BUS
I/O BUS AND
COLUMN DECODER
I/O BUS AND
COLUMN DECODER
VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC NC NC LCAS UCAS OE A8 A7 A6 A5 A4 VSS
VCC
A3 A2 A1 A0
NC
RAS
WE
NC NC NC NC
I/O7 I/O6 I/O5 I/O4 VCC I/O3 I/O2 I/O1 I/O0 VCC
START/
STOP
LOGIC
DATA WORD
ADDRESS/
COUNTER
X
DECODER
DEVICE
ADDRESS
COMPARATOR
LOAD
COMP
SERIAL
CONTROL
LOGIC
DATA
RECOVERY
H.V.
PUMP/
TIMING
D OUT/
ACK
LOGIC
Y
DECODER
EEPROM
SERIAL
MUX
1
2
3
4
5
6
7
8
D OUT
D IN
R/W
LOAD
INC
EN
A0
A1
A2
VSS
VCC
WP
SCL
SDA
IC302 AT24C32N-10SI-TR
IC306 MM1284XFFE
RESET
SW
SW
SW
1
2
3
4
5
6
7 8
9
10
14
13
12
11
VCC
BUS ON
LINK OFF
CLK OUT
DATA OUT
DATA IN
RESET
BUS RESET
BUS DATA
VREF
BUS CLK
GND
BUS ON INPUT
BUS ON OUT
CONTROL
CIRCUIT
LOW VCC
DETECTOR CIRCUIT
WRITE/ERASE
PULSE TIMER
ERASE CIRCUIT
CHIP ENABLE/
OUTPUT ENABLE
CIRCUIT
I/O
BUFFER
DATA
LATCH
ADDRESS
LATCH
Y
DECODER
16,777,216
CELL
MATRIX
Y GATE
WRITE CIRCUIT
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
VSS
VSS
VCC
DQ4
DQ5
DQ6
DQ7
WE
OE
RY/BY
DQ3
DQ2
DQ1
DQ0
A0
A1
NC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
21
22
A14
A15
A19
A18
A17
NC
A11
CE
A8
A7
A5
A6
A13
VCC
RESET
A12
47
48
45
46
A4
NC
NC
A9
A16
A10
X
DECODER
NC
NC
A20
NC
NC
STB
STB
NC
NC
A2
A3
IC401 MBM29F016-90PFTN-DSP02L
IC402 MBM29F016-90PFTN-DSP02H