Sony XES-Z50, Service Manual, Page: 81 / 153

XES-Z50
7-7. BLOCK DIAGRAM – CHANGER UNIT (CD Section (2/2)) –
– 85 – – 86 –
10
9
11
13
8
3
5
6
7
1
79
80
2
61 62 74 64 60 58 59 63
47
46
38
37
45
36
16
25
23
24
26
23 4 3 22
23 4
3 22
25 46 28 24 26 22 23 27
49
50
48
45
44
43
30
64
32 31 39 38 47 4
5 6
78
28
56
4
5
7
6
30
29
76
77
8
9
62
63 29
22
30
24
1
6
2
3
7
8
5
9
10
11
12
DATA, BCLK DATA
BCLK
LRCK
WDCK
DATAI
BCKI
LRCI
WDCI
GTOP
RFCK
WFCK
SCOR
WFCK
SCOR
GRSRST
GRSCOR
RAOF
GTOP
RFCK
XROI
LRCK, WDCK
GTOP,
RFCK, RAOF
C16M C4M
20 – 27
11 – 18, 64 – 69, 74, 75, 60
13 – 15, 17 – 21
12 – 5, 27, 26, 23, 25, 4, 28, 3, 31, 2
42, 41, 44, 43
30 – 27, 55 – 53, 51, 50, 31
1, 2, 24, 25 9 – 12, 14 – 18, 5
1, 2, 24, 25 9 – 12, 14 – 18, 5
XRST
CDRST
DATA, CLK
WFCK, SCOR,
EXCK, SBSO
DIGITAL
SIGNAL
PROCESSOR
INTERFACE
DATA
LINKING
CONTROL
SELECTOR
D-RAM INTERFACE
READ/WRITE
BASE
COUNTER
VWA
ADDRESS
MONITOR
CPU INTERFACE
SDTI SCK SDTO XQOK ESPXLT XWRE XRDE XSOE
DATA CLK DATA XQOK LATCH XWRE XRDE XSOE
DATA XQOK
LATCH
XWRE
XRDE XSOE
SDTI
XQOK
GRSRST
GRSCORE
ESPXTL
EECLK EEDATA TEMP H TEMP L XTLI XTLO
XWRE
XRDE XSOE
SYSTEM CONTROLLER
IC301 (2/3)
X301
8MHz
TH302 TH301
CLK
DATA
EEPROM
IC302
05
+5V
RESET SIGNAL
GENERATOR
IC903
BU. CHECK
RESET
RSTO
BUSY
REQ
CCLK
CSI
CSO
D303
SSI
SCLK
WFCK
SCOR
EXTAL
XTAL
CSI
CSO
CCLK
REQ
BUSY
RST
BUCK
SBSO
EXCK
WFCK
SCOR
X302
10MHz
ADD0 – ADD16
DATA0 – DATA7
D0 – D7
A0 – A16
WE
CE
+5V
OE
CE2
CE1
WE
S-RAM
IC304
CD TEXT DECODER
IC303
D-RAM
IC403
A0 – A9
A0 – A9
D1 – D4
D1 – D4
A0 – A9 D1 – D4
XCAS
XRAS
XWE
XOE
XCAS XRAS XWE XOE
DATA BUS
ADDRESS BUS
OE1
WE1
RAS
CAS
WE2
OE2
BATTERY CHECK
RST
XRAS
XCAS
XWE
XWE2
XOE
XOE2
RAS
CAS
WE1
WE2
OE1
OE2
D-RAM
IC402
CLOCK
GENERATOR
IC503
BUFFER
IC504
XTAI TIMING
GENERATOR
D/A
CONVERTER
INTERFACE
DATA
D OUT
BCK
LRCK
DATA
BCK
LRCK
D-RAM CONTROLLER
IC401
DIGITAL
OUT
DATA,
BCK, LRCK
SYNC (44.1kHz)
(Page 87)
(Page 87)
(Page 93)
(Page 93)
•
Signal path.
: CD PLAY
(Page 84)
(Page 84)
(Page 84)
(Page 84)
(Page 84)
(Page 84)
(Page 84)